split NOR and NAND flash headers

[openocd.git] / src / target / arm_dpm.c

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index f94fcc4e0962b900b68c367edb3def8cf1c93a43..a9ce880719453024dd1856357d27f79e68bbdda6 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -23,7 +23,7 @@
 
 #include "armv4_5.h"           /* REVISIT to become arm.h */
 #include "arm_dpm.h"
-#include "jtag.h"
+#include <jtag/jtag.h>
 #include "register.h"
 #include "breakpoints.h"
 #include "target_type.h"
@@ -55,7 +55,9 @@ static int dpm_mrc(struct target *target, int cpnum,
        if (retval != ERROR_OK)
                return retval;
 
-       LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
+       LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
+                       (int) op1, (int) CRn,
+                       (int) CRm, (int) op2);
 
        /* read coprocessor register into R0; return via DCC */
        retval = dpm->instr_read_data_r0(dpm,
@@ -78,7 +80,9 @@ static int dpm_mcr(struct target *target, int cpnum,
        if (retval != ERROR_OK)
                return retval;
 
-       LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
+       LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
+                       (int) op1, (int) CRn,
+                       (int) CRm, (int) op2);
 
        /* read DCC into r0; then write coprocessor register from R0 */
        retval = dpm->instr_write_data_r0(dpm,
@@ -276,6 +280,7 @@ fail:
  * Writes all modified core registers for all processor modes.  In normal
  * operation this is called on exit from halting debug state.
  *
+ * @param dpm: represents the processor
  * @param bpwp: true ensures breakpoints and watchpoints are set,
  *     false ensures they are cleared
  */
@@ -736,6 +741,59 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
        return retval;
 }
 
+void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
+{
+       switch (dpm->arm->core_state) {
+       case ARMV4_5_STATE_ARM:
+               addr -= 8;
+               break;
+       case ARMV4_5_STATE_THUMB:
+       case ARM_STATE_THUMB_EE:
+               addr -= 4;
+               break;
+       case ARMV4_5_STATE_JAZELLE:
+               /* ?? */
+               break;
+       }
+       dpm->wp_pc = addr;
+}
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Other debug and support utilities
+ */
+
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
+{
+       struct target *target = dpm->arm->target;
+
+       dpm->dscr = dscr;
+
+       /* Examine debug reason */
+       switch (DSCR_ENTRY(dscr)) {
+       case 6:         /* Data abort (v6 only) */
+       case 7:         /* Prefetch abort (v6 only) */
+               /* FALL THROUGH -- assume a v6 core in abort mode */
+       case 0:         /* HALT request from debugger */
+       case 4:         /* EDBGRQ */
+               target->debug_reason = DBG_REASON_DBGRQ;
+               break;
+       case 1:         /* HW breakpoint */
+       case 3:         /* SW BKPT */
+       case 5:         /* vector catch */
+               target->debug_reason = DBG_REASON_BREAKPOINT;
+               break;
+       case 2:         /* asynch watchpoint */
+       case 10:        /* precise watchpoint */
+               target->debug_reason = DBG_REASON_WATCHPOINT;
+               break;
+       default:
+               target->debug_reason = DBG_REASON_UNDEFINED;
+               break;
+       }
+}
+
 /*----------------------------------------------------------------------*/
 
 /*
@@ -790,18 +848,6 @@ int arm_dpm_setup(struct arm_dpm *dpm)
                return ERROR_FAIL;
        }
 
-       /* Disable all breakpoints and watchpoints at startup. */
-       if (dpm->bpwp_disable) {
-               unsigned i;
-
-               for (i = 0; i < dpm->nbp; i++)
-                       (void) dpm->bpwp_disable(dpm, i);
-               for (i = 0; i < dpm->nwp; i++)
-                       (void) dpm->bpwp_disable(dpm, 16 + i);
-       } else
-               LOG_WARNING("%s: can't disable breakpoints and watchpoints",
-                       target_name(target));
-
        LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
                        target_name(target), dpm->nbp, dpm->nwp);
 
@@ -818,6 +864,17 @@ int arm_dpm_setup(struct arm_dpm *dpm)
  */
 int arm_dpm_initialize(struct arm_dpm *dpm)
 {
-       /* FIXME -- nothing yet */
+       /* Disable all breakpoints and watchpoints at startup. */
+       if (dpm->bpwp_disable) {
+               unsigned i;
+
+               for (i = 0; i < dpm->nbp; i++)
+                       (void) dpm->bpwp_disable(dpm, i);
+               for (i = 0; i < dpm->nwp; i++)
+                       (void) dpm->bpwp_disable(dpm, 16 + i);
+       } else
+               LOG_WARNING("%s: can't disable breakpoints and watchpoints",
+                       target_name(dpm->arm->target));
+
        return ERROR_OK;
 }