+#define DSCR_CORE_HALTED (0x1 << 0)
+#define DSCR_CORE_RESTARTED (0x1 << 1)
+#define DSCR_ENTRY_MASK (0xF << 2)
+#define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
+#define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
+#define DSCR_STICKY_UNDEFINED (0x1 << 8)
+#define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */
+#define DSCR_DBG_ACK (0x1 << 10)
+#define DSCR_INT_DIS (0x1 << 11)
+#define DSCR_CP14_USR_COMMS (0x1 << 12)
+#define DSCR_ITR_EN (0x1 << 13)
+#define DSCR_HALT_DBG_MODE (0x1 << 14)
+#define DSCR_MON_DBG_MODE (0x1 << 15)
+#define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
+#define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
+#define DSCR_NON_SECURE (0x1 << 18)
+#define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
+#define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
+#define DSCR_INSTR_COMP (0x1 << 24)
+#define DSCR_PIPE_ADVANCE (0x1 << 25)
+#define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
+#define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */
+#define DSCR_DTR_TX_FULL (0x1 << 29)
+#define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
+
+#define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
+#define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
+
+
+/* Methods of entry into debug mode */
+#define DSCR_ENTRY_HALT_REQ (0x03)
+#define DSCR_ENTRY_BREAKPOINT (0x07)
+#define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
+#define DSCR_ENTRY_BKPT_INSTR (0x0F)
+#define DSCR_ENTRY_EXT_DBG_REQ (0x13)
+#define DSCR_ENTRY_VECT_CATCH (0x17)
+#define DSCR_ENTRY_D_SIDE_ABORT (0x1B) /* v6 only */
+#define DSCR_ENTRY_I_SIDE_ABORT (0x1F) /* v6 only */
+#define DSCR_ENTRY_OS_UNLOCK (0x23)
+#define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
+
+/* DTR modes */
+#define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
+#define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
+#define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
+
+
+
+
+
+/* DRCR (debug run control register) bits */
+#define DRCR_HALT (1 << 0)
+#define DRCR_RESTART (1 << 1)
+#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
+
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+
+/* PRCR (Device Power-down and Reset Control Register) bits */
+#define PRCR_DEBUG_NO_POWER_DOWN (1 << 0)
+#define PRCR_WARM_RESET (1 << 1)
+#define PRCR_HOLD_NON_DEBUG_RESET (1 << 2)
+
+/* PRSR (Device Power-down and Reset Status Register) bits */
+#define PRSR_POWERUP_STATUS (1 << 0)
+#define PRSR_STICKY_POWERDOWN_STATUS (1 << 1)
+#define PRSR_RESET_STATUS (1 << 2)
+#define PRSR_STICKY_RESET_STATUS (1 << 3)
+#define PRSR_HALTED (1 << 4) /* v7.1 Debug only */
+#define PRSR_OSLK (1 << 5) /* v7.1 Debug only */
+#define PRSR_DLK (1 << 6) /* v7.1 Debug only */
+
+/* OSLSR (OS Lock Status Register) bits */
+#define OSLSR_OSLM0 (1 << 0)
+#define OSLSR_OSLK (1 << 1)
+#define OSLSR_NTT (1 << 2)
+#define OSLSR_OSLM1 (1 << 3)
+#define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)
+
+#endif /* OPENOCD_TARGET_ARM_DPM_H */