+#define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
+
+/* Copies two words from two ARM core registers
+ * into a doubleword extension register, or
+ * from a doubleword extension register to two ARM core registers.
+ * See Armv7-A arch reference manual section A8.8.345
+ * rt: Arm core register 1
+ * rt2: Arm core register 2
+ * vm: The doubleword extension register
+ * m: m = UInt(m:vm);
+ * op: to_arm_registers = (op == ‘1’);
+ */
+#define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
+ (0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
+ ((rt) << 12) | ((m) << 5) | (vm))
+
+/* Moves the value of the FPSCR to an ARM core register
+ * rt: Arm core register
+ */
+#define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
+
+/* Moves the value of an ARM core register to the FPSCR.
+ * rt: Arm core register
+ */
+#define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
+
+/* Store data from coprocessor to consecutive memory
+ * See Armv7-A arch doc section A8.6.187
+ * p: 1=index mode (offset from rn)
+ * u: 1=add, 0=subtract rn address with imm
+ * d: Opcode D encoding
+ * w: write back the offset start address to the rn register
+ * cp: Coprocessor number (4 bits)
+ * crd: Coprocessor source register (4 bits)
+ * rn: Base register for memory address (4 bits)
+ * imm: Immediate value (0 - 1020, must be divisible by 4)
+ */
+#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
+ (0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
+ ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
+
+/* Loads data from consecutive memory to coprocessor
+ * See Armv7-A arch doc section A8.6.51
+ * p: 1=index mode (offset from rn)
+ * u: 1=add, 0=subtract rn address with imm
+ * d: Opcode D encoding
+ * w: write back the offset start address to the rn register
+ * cp: Coprocessor number (4 bits)
+ * crd: Coprocessor dest register (4 bits)
+ * rn: Base register for memory address (4 bits)
+ * imm: Immediate value (0 - 1020, must be divisible by 4)
+ */
+#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
+ (0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
+ ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))