Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
target/arm_semihosting: Use 'bool' data type
[openocd.git] / src / target / arm_semihosting.c
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 57f3139c2bae1b4b8a84ac17499df86582974870..61f1e7801f443b5daa3044f0db491a3bc681c3f1 100644 (file)
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -46,6 +46,7 @@
 #include "arm7_9_common.h"
 #include "armv7m.h"
 #include "armv7a.h"
+#include "armv8.h"
 #include "cortex_m.h"
 #include "register.h"
 #include "arm_opcodes.h"
@@ -55,10 +56,35 @@
 #include <helper/log.h>
 #include <sys/stat.h>
 
+static int arm_semihosting_resume(struct target *target, int *retval)
+{
+       if (is_armv8(target_to_armv8(target))) {
+               struct armv8_common *armv8 = target_to_armv8(target);
+               if (armv8->last_run_control_op == ARMV8_RUNCONTROL_RESUME) {
+                       *retval = target_resume(target, 1, 0, 0, 0);
+                       if (*retval != ERROR_OK) {
+                               LOG_ERROR("Failed to resume target");
+                               return 0;
+                       }
+               } else if (armv8->last_run_control_op == ARMV8_RUNCONTROL_STEP)
+                       target->debug_reason = DBG_REASON_SINGLESTEP;
+       } else {
+               *retval = target_resume(target, 1, 0, 0, 0);
+               if (*retval != ERROR_OK) {
+                       LOG_ERROR("Failed to resume target");
+                       return 0;
+               }
+       }
+       return 1;
+}
+
 static int post_result(struct target *target)
 {
        struct arm *arm = target_to_arm(target);
 
+       if (!target->semihosting)
+               return ERROR_FAIL;
+
        /* REVISIT this looks wrong ... ARM11 and Cortex-A8
         * should work this way at least sometimes.
         */
@@ -68,12 +94,12 @@ static int post_result(struct target *target)
 
                /* return value in R0 */
                buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
-               arm->core_cache->reg_list[0].dirty = 1;
+               arm->core_cache->reg_list[0].dirty = true;
 
                /* LR --> PC */
                buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32,
                        buf_get_u32(arm_reg_current(arm, 14)->value, 0, 32));
-               arm->core_cache->reg_list[15].dirty = 1;
+               arm->core_cache->reg_list[15].dirty = true;
 
                /* saved PSR --> current PSR */
                spsr = buf_get_u32(arm->spsr->value, 0, 32);
@@ -83,18 +109,28 @@ static int post_result(struct target *target)
                 */
 
                buf_set_u32(arm->cpsr->value, 0, 32, spsr);
-               arm->cpsr->dirty = 1;
+               arm->cpsr->dirty = true;
                arm->core_mode = spsr & 0x1f;
                if (spsr & 0x20)
                        arm->core_state = ARM_STATE_THUMB;
 
+       } else if (is_armv8(target_to_armv8(target))) {
+               if (arm->core_state == ARM_STATE_AARCH64) {
+                       /* return value in R0 */
+                       buf_set_u64(arm->core_cache->reg_list[0].value, 0, 64, target->semihosting->result);
+                       arm->core_cache->reg_list[0].dirty = true;
+
+                       uint64_t pc = buf_get_u64(arm->core_cache->reg_list[32].value, 0, 64);
+                       buf_set_u64(arm->pc->value, 0, 64, pc + 4);
+                       arm->pc->dirty = true;
+               }
        } else {
                /* resume execution, this will be pc+2 to skip over the
                 * bkpt instruction */
 
                /* return result in R0 */
                buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
-               arm->core_cache->reg_list[0].dirty = 1;
+               arm->core_cache->reg_list[0].dirty = true;
        }
 
        return ERROR_OK;
@@ -235,6 +271,24 @@ int arm_semihosting(struct target *target, int *retval)
                /* bkpt 0xAB */
                if (insn != 0xBEAB)
                        return 0;
+       } else if (is_armv8(target_to_armv8(target))) {
+               if (target->debug_reason != DBG_REASON_BREAKPOINT)
+                       return 0;
+
+               if (arm->core_state == ARM_STATE_AARCH64) {
+                       uint32_t insn = 0;
+                       r = arm->pc;
+                       uint64_t pc64 = buf_get_u64(r->value, 0, 64);
+                       *retval = target_read_u32(target, pc64, &insn);
+
+                       if (*retval != ERROR_OK)
+                               return 1;
+
+                       /* bkpt 0xAB */
+                       if (insn != 0xD45E0000)
+                               return 0;
+               } else
+                       return 1;
        } else {
                LOG_ERROR("Unsupported semi-hosting Target");
                return 0;
@@ -244,13 +298,18 @@ int arm_semihosting(struct target *target, int *retval)
         * operation to complete.
         */
        if (!semihosting->hit_fileio) {
-               /* TODO: update for 64-bits */
-               uint32_t r0 = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
-               uint32_t r1 = buf_get_u32(arm->core_cache->reg_list[1].value, 0, 32);
-
-               semihosting->op = r0;
-               semihosting->param = r1;
-               semihosting->word_size_bytes = 4;
+               if (is_armv8(target_to_armv8(target)) &&
+                               arm->core_state == ARM_STATE_AARCH64) {
+                       /* Read op and param from register x0 and x1 respectively. */
+                       semihosting->op = buf_get_u64(arm->core_cache->reg_list[0].value, 0, 64);
+                       semihosting->param = buf_get_u64(arm->core_cache->reg_list[1].value, 0, 64);
+                       semihosting->word_size_bytes = 8;
+               } else {
+                       /* Read op and param from register r0 and r1 respectively. */
+                       semihosting->op = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
+                       semihosting->param = buf_get_u32(arm->core_cache->reg_list[1].value, 0, 32);
+                       semihosting->word_size_bytes = 4;
+               }
 
                /* Check for ARM operation numbers. */
                if (0 <= semihosting->op && semihosting->op <= 0x31) {
@@ -265,19 +324,11 @@ int arm_semihosting(struct target *target, int *retval)
                }
        }
 
-       /* Post result to target if we are not waiting on a fileio
+       /* Resume if target it is resumable and we are not waiting on a fileio
         * operation to complete:
         */
-       if (semihosting->is_resumable && !semihosting->hit_fileio) {
-               /* Resume right after the BRK instruction. */
-               *retval = target_resume(target, 1, 0, 0, 0);
-               if (*retval != ERROR_OK) {
-                       LOG_ERROR("Failed to resume target");
-                       return 0;
-               }
-
-               return 1;
-       }
+       if (semihosting->is_resumable && !semihosting->hit_fileio)
+               return arm_semihosting_resume(target, retval);
 
        return 0;
 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)