#include "config.h"
#endif
-#include "target.h"
#include "armv4_5.h"
#include "arm_disassembler.h"
#include "arm_simulator.h"
#include "log.h"
#include "binarybuffer.h"
-#include <string.h>
-u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
+uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *carry)
{
- u32 return_value = 0;
+ uint32_t return_value = 0;
shift_amount &= 0xff;
-
+
if (shift == 0x0) /* LSL */
{
if ((shift_amount > 0) && (shift_amount <= 32))
Rm |= 0x80000000;
*carry = Rm & 0x1;
}
-
+
return return_value;
}
-u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, u8 *shifter_carry_out)
+
+uint32_t arm_shifter_operand(struct arm_sim_interface *sim, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out)
{
- u32 return_value;
+ uint32_t return_value;
int instruction_size;
-
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+
+ if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
instruction_size = 4;
else
instruction_size = 2;
-
- *shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
-
+
+ *shifter_carry_out = sim->get_cpsr(sim, 29, 1);
+
if (variant == 0) /* 32-bit immediate */
{
return_value = shifter_operand.immediate.immediate;
}
else if (variant == 1) /* immediate shift */
{
- u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32);
-
+ uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm);
+
/* adjust RM in case the PC is being read */
if (shifter_operand.immediate_shift.Rm == 15)
Rm += 2 * instruction_size;
-
+
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out);
}
else if (variant == 2) /* register shift */
{
- u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32);
- u32 Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32);
-
+ uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm);
+ uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs);
+
/* adjust RM in case the PC is being read */
if (shifter_operand.register_shift.Rm == 15)
Rm += 2 * instruction_size;
-
+
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out);
}
else
LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff;
}
-
+
return return_value;
}
-int pass_condition(u32 cpsr, u32 opcode)
+int pass_condition(uint32_t cpsr, uint32_t opcode)
{
switch ((opcode & 0xf0000000) >> 28)
{
else
return 0;
case 0xd: /* LE */
- if ((cpsr & 0x40000000) &&
- (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
- || (!(cpsr & 0x80000000) && (cpsr & 0x10000000))))
+ if ((cpsr & 0x40000000) ||
+ ((cpsr & 0x80000000) && !(cpsr & 0x10000000))
+ || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xe:
case 0xf:
return 1;
-
+
}
-
+
LOG_ERROR("BUG: should never get here");
return 0;
}
-int thumb_pass_branch_condition(u32 cpsr, u16 opcode)
+int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
{
- return pass_condition(cpsr, (opcode & 0x0f00) << 20);
+ return pass_condition(cpsr, (opcode & 0x0f00) << 20);
}
/* simulate a single step (if possible)
* if the dry_run_pc argument is provided, no state is changed,
* but the new pc is stored in the variable pointed at by the argument
*/
-int arm_simulate_step(target_t *target, u32 *dry_run_pc)
+int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_sim_interface *sim)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ uint32_t current_pc = sim->get_reg(sim, 15);
arm_instruction_t instruction;
int instruction_size;
int retval = ERROR_OK;
-
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+
+ if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
{
- u32 opcode;
-
+ uint32_t opcode;
+
/* get current instruction, and identify it */
- if((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
+ if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
{
return retval;
}
- if((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
+ if ((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
{
return retval;
}
instruction_size = 4;
-
+
/* check condition code (for all instructions) */
- if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
+ if (!pass_condition(sim->get_cpsr(sim, 0, 32), opcode))
{
if (dry_run_pc)
{
}
else
{
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+ sim->set_reg(sim, 15, current_pc + instruction_size);
}
-
+
return ERROR_OK;
}
}
else
{
- u16 opcode;
-
- if((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
- {
+ uint16_t opcode;
+
+ retval = target_read_u16(target, current_pc, &opcode);
+ if (retval != ERROR_OK)
return retval;
- }
- if((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
- {
+ retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+ if (retval != ERROR_OK)
return retval;
- }
instruction_size = 2;
-
- /* check condition code (only for branch instructions) */
- if ((!thumb_pass_branch_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) &&
- (instruction.type == ARM_B))
+
+ /* check condition code (only for branch (1) instructions) */
+ if ((opcode & 0xf000) == 0xd000 &&
+ !thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode))
{
if (dry_run_pc)
{
}
else
{
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+ sim->set_reg(sim, 15, current_pc + instruction_size);
}
-
+
return ERROR_OK;
}
+
+ /* Deal with 32-bit BL/BLX */
+ if ((opcode & 0xf800) == 0xf000) {
+ uint32_t high = instruction.info.b_bl_bx_blx.target_address;
+ retval = target_read_u16(target, current_pc+2, &opcode);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+ if (retval != ERROR_OK)
+ return retval;
+ instruction.info.b_bl_bx_blx.target_address += high;
+ }
}
-
+
/* examine instruction type */
/* branch instructions */
if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
{
- u32 target;
-
+ uint32_t target;
+
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
{
target = instruction.info.b_bl_bx_blx.target_address;
}
else
{
- target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
- if(instruction.info.b_bl_bx_blx.reg_operand == 15)
+ target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
+ if (instruction.info.b_bl_bx_blx.reg_operand == 15)
{
target += 2 * instruction_size;
}
}
-
+
if (dry_run_pc)
- {
- *dry_run_pc = target;
+ {
+ *dry_run_pc = target & ~1;
return ERROR_OK;
}
else
{
if (instruction.type == ARM_B)
{
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
+ sim->set_reg(sim, 15, target);
}
else if (instruction.type == ARM_BL)
{
- u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
+ uint32_t old_pc = sim->get_reg(sim, 15);
+ int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+ sim->set_reg_mode(sim, 14, old_pc + 4 + T);
+ sim->set_reg(sim, 15, target);
}
else if (instruction.type == ARM_BX)
{
if (target & 0x1)
{
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
}
else
{
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
}
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
+ sim->set_reg(sim, 15, target & 0xfffffffe);
}
else if (instruction.type == ARM_BLX)
{
- u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
+ uint32_t old_pc = sim->get_reg(sim, 15);
+ int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+ sim->set_reg_mode(sim, 14, old_pc + 4 + T);
if (target & 0x1)
{
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
}
else
{
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
}
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
+ sim->set_reg(sim, 15, target & 0xfffffffe);
}
-
+
return ERROR_OK;
}
}
else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
{
- u32 Rd, Rn, shifter_operand;
- u8 C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
- u8 carry_out;
-
+ uint32_t Rd, Rn, shifter_operand;
+ uint8_t C = sim->get_cpsr(sim, 29, 1);
+ uint8_t carry_out;
+
Rd = 0x0;
/* ARM_MOV and ARM_MVN does not use Rn */
if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
- Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+ Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn);
else
Rn = 0;
- shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
+ shifter_operand = arm_shifter_operand(sim, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
/* adjust Rn in case the PC is being read */
if (instruction.info.data_proc.Rn == 15)
Rn += 2 * instruction_size;
-
+
if (instruction.type == ARM_AND)
Rd = Rn & shifter_operand;
else if (instruction.type == ARM_EOR)
Rd = ~shifter_operand;
else
LOG_WARNING("unhandled instruction type");
-
+
if (dry_run_pc)
{
if (instruction.info.data_proc.Rd == 15)
- {
- *dry_run_pc = Rd;
- return ERROR_OK;
- }
+ *dry_run_pc = Rd & ~1;
else
- {
*dry_run_pc = current_pc + instruction_size;
- }
-
+
return ERROR_OK;
}
else
{
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
- LOG_WARNING("no updating of flags yet");
-
- if (instruction.info.data_proc.Rd == 15)
+ if (instruction.info.data_proc.Rd == 15) {
+ sim->set_reg_mode(sim, 15, Rd & ~1);
+ if (Rd & 1)
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ else
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
return ERROR_OK;
+ }
+ sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
+ LOG_WARNING("no updating of flags yet");
}
}
/* compare instructions (CMP, CMN, TST, TEQ) */
/* load register instructions */
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
{
- u32 load_address = 0, modified_address = 0, load_value;
- u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
-
+ uint32_t load_address = 0, modified_address = 0, load_value;
+ uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
+
/* adjust Rn in case the PC is being read */
if (instruction.info.load_store.Rn == 15)
Rn += 2 * instruction_size;
-
+
if (instruction.info.load_store.offset_mode == 0)
{
if (instruction.info.load_store.U)
}
else if (instruction.info.load_store.offset_mode == 1)
{
- u32 offset;
- u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.offset.reg.Rm).value, 0, 32);
- u8 shift = instruction.info.load_store.offset.reg.shift;
- u8 shift_imm = instruction.info.load_store.offset.reg.shift_imm;
- u8 carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
-
+ uint32_t offset;
+ uint32_t Rm = sim->get_reg_mode(sim, instruction.info.load_store.offset.reg.Rm);
+ uint8_t shift = instruction.info.load_store.offset.reg.shift;
+ uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
+ uint8_t carry = sim->get_cpsr(sim, 29, 1);
+
offset = arm_shift(shift, Rm, shift_imm, &carry);
-
+
if (instruction.info.load_store.U)
modified_address = Rn + offset;
else
{
LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
}
-
+
if (instruction.info.load_store.index_mode == 0)
{
/* offset mode
* we load from the unmodified address, and write the modified address back */
load_address = Rn;
}
-
- if((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
+
+ if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
{
- if((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
+ if ((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
{
return retval;
}
}
-
+
if (dry_run_pc)
{
if (instruction.info.load_store.Rd == 15)
- {
- *dry_run_pc = load_value;
- return ERROR_OK;
- }
+ *dry_run_pc = load_value & ~1;
else
- {
*dry_run_pc = current_pc + instruction_size;
- }
-
return ERROR_OK;
}
else
if ((instruction.info.load_store.index_mode == 1) ||
(instruction.info.load_store.index_mode == 2))
{
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32, modified_address);
- }
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rd).value, 0, 32, load_value);
-
- if (instruction.info.load_store.Rd == 15)
+ sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
+ }
+
+ if (instruction.info.load_store.Rd == 15) {
+ sim->set_reg_mode(sim, 15, load_value & ~1);
+ if (load_value & 1)
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ else
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
return ERROR_OK;
+ }
+ sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
}
}
/* load multiple instruction */
else if (instruction.type == ARM_LDM)
{
int i;
- u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32);
- u32 load_values[16];
+ uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
+ uint32_t load_values[16];
int bits_set = 0;
for (i = 0; i < 16; i++)
if (instruction.info.load_store_multiple.register_list & (1 << i))
bits_set++;
}
-
+
switch (instruction.info.load_store_multiple.addressing_mode)
{
case 0: /* Increment after */
Rn = Rn + 4;
break;
case 2: /* Decrement after */
- Rn = Rn - (bits_set * 4) + 4;
+ Rn = Rn - (bits_set * 4) + 4;
break;
case 3: /* Decrement before */
Rn = Rn - (bits_set * 4);
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
- if((!dry_run_pc) || (i == 15))
+ if ((!dry_run_pc) || (i == 15))
{
target_read_u32(target, Rn, &load_values[i]);
}
Rn += 4;
}
}
-
+
if (dry_run_pc)
{
if (instruction.info.load_store_multiple.register_list & 0x8000)
{
- *dry_run_pc = load_values[15];
+ *dry_run_pc = load_values[15] & ~1;
return ERROR_OK;
}
}
else
{
- enum armv4_5_mode mode = armv4_5->core_mode;
+ enum armv4_5_mode mode = sim->get_mode(sim);
int update_cpsr = 0;
if (instruction.info.load_store_multiple.S)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, i).value, 0, 32, load_values[i]);
+ if (i == 15) {
+ uint32_t val = load_values[i];
+ sim->set_reg_mode(sim, i, val & ~1);
+ if (val & 1)
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ else
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
+ } else {
+ sim->set_reg_mode(sim, i, load_values[i]);
+ }
}
}
-
+
if (update_cpsr)
{
- u32 spsr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32);
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
+ uint32_t spsr = sim->get_reg_mode(sim, 16);
+ sim->set_reg(sim, ARMV4_5_CPSR, spsr);
}
-
+
/* base register writeback */
if (instruction.info.load_store_multiple.W)
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
-
+ sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
+
if (instruction.info.load_store_multiple.register_list & 0x8000)
return ERROR_OK;
}
}
else
{
- u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32);
+ uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
int bits_set = 0;
- enum armv4_5_mode mode = armv4_5->core_mode;
+ enum armv4_5_mode mode = sim->get_mode(sim);
for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
bits_set++;
}
-
+
if (instruction.info.load_store_multiple.S)
{
mode = ARMV4_5_MODE_USR;
}
-
+
switch (instruction.info.load_store_multiple.addressing_mode)
{
case 0: /* Increment after */
Rn = Rn + 4;
break;
case 2: /* Decrement after */
- Rn = Rn - (bits_set * 4) + 4;
+ Rn = Rn - (bits_set * 4) + 4;
break;
case 3: /* Decrement before */
Rn = Rn - (bits_set * 4);
break;
}
-
+
for (i = 0; i < 16; i++)
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
- target_write_u32(target, Rn, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32));
+ target_write_u32(target, Rn, sim->get_reg_mode(sim, i));
Rn += 4;
}
}
-
+
/* base register writeback */
if (instruction.info.load_store_multiple.W)
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
-
+ sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
+
}
}
else if (!dry_run_pc)
{
/* the instruction wasn't handled, but we're supposed to simulate it
*/
- return ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED;
+ LOG_ERROR("Unimplemented instruction, could not simulate it.");
+ return ERROR_FAIL;
}
-
+
if (dry_run_pc)
{
*dry_run_pc = current_pc + instruction_size;
}
else
{
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+ sim->set_reg(sim, 15, current_pc + instruction_size);
return ERROR_OK;
}
-
+
+}
+
+static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
+}
+
+static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
+}
+
+static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32);
}
+
+static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32, value);
+}
+
+static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
+}
+
+static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return armv4_5->core_state;
+}
+
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ armv4_5->core_state = mode;
+}
+
+
+static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return armv4_5->core_mode;
+}
+
+
+
+int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
+{
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm_sim_interface sim;
+
+ sim.user_data = armv4_5;
+ sim.get_reg = &armv4_5_get_reg;
+ sim.set_reg = &armv4_5_set_reg;
+ sim.get_reg_mode = &armv4_5_get_reg_mode;
+ sim.set_reg_mode = &armv4_5_set_reg_mode;
+ sim.get_cpsr = &armv4_5_get_cpsr;
+ sim.get_mode = &armv4_5_get_mode;
+ sim.get_state = &armv4_5_get_state;
+ sim.set_state = &armv4_5_set_state;
+
+ return arm_simulate_step_core(target, dry_run_pc, &sim);
+}
+
Code Review / openocd.git / blobdiff