#include "register.h"
-static const char *armv4_5_core_reg_list[] =
-{
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
+static const uint8_t arm_usr_indices[17] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
+};
- "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
+static const uint8_t arm_fiq_indices[8] = {
+ 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
+};
- "r13_irq", "lr_irq",
+static const uint8_t arm_irq_indices[3] = {
+ 23, 24, ARMV4_5_SPSR_IRQ,
+};
- "r13_svc", "lr_svc",
+static const uint8_t arm_svc_indices[3] = {
+ 25, 26, ARMV4_5_SPSR_SVC,
+};
- "r13_abt", "lr_abt",
+static const uint8_t arm_abt_indices[3] = {
+ 27, 28, ARMV4_5_SPSR_ABT,
+};
- "r13_und", "lr_und",
+static const uint8_t arm_und_indices[3] = {
+ 29, 30, ARMV4_5_SPSR_UND,
+};
- "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
+static const uint8_t arm_mon_indices[3] = {
+ 37, 38, ARM_SPSR_MON,
};
static const struct {
const char *name;
- unsigned psr;
+ unsigned short psr;
+ /* For user and system modes, these list indices for all registers.
+ * otherwise they're just indices for the shadow registers and SPSR.
+ */
+ unsigned short n_indices;
+ const uint8_t *indices;
} arm_mode_data[] = {
/* Seven modes are standard from ARM7 on. "System" and "User" share
* the same registers; other modes shadow from 3 to 8 registers.
{
.name = "User",
.psr = ARMV4_5_MODE_USR,
+ .n_indices = ARRAY_SIZE(arm_usr_indices),
+ .indices = arm_usr_indices,
},
{
.name = "FIQ",
.psr = ARMV4_5_MODE_FIQ,
+ .n_indices = ARRAY_SIZE(arm_fiq_indices),
+ .indices = arm_fiq_indices,
},
{
.name = "Supervisor",
.psr = ARMV4_5_MODE_SVC,
+ .n_indices = ARRAY_SIZE(arm_svc_indices),
+ .indices = arm_svc_indices,
},
{
.name = "Abort",
.psr = ARMV4_5_MODE_ABT,
+ .n_indices = ARRAY_SIZE(arm_abt_indices),
+ .indices = arm_abt_indices,
},
{
.name = "IRQ",
.psr = ARMV4_5_MODE_IRQ,
+ .n_indices = ARRAY_SIZE(arm_irq_indices),
+ .indices = arm_irq_indices,
},
{
- .name = "Undefined" /* instruction */,
+ .name = "Undefined instruction",
.psr = ARMV4_5_MODE_UND,
+ .n_indices = ARRAY_SIZE(arm_und_indices),
+ .indices = arm_und_indices,
},
{
.name = "System",
.psr = ARMV4_5_MODE_SYS,
+ .n_indices = ARRAY_SIZE(arm_usr_indices),
+ .indices = arm_usr_indices,
},
/* TrustZone "Security Extensions" add a secure monitor mode.
* This is distinct from a "debug monitor" which can support
{
.name = "Secure Monitor",
.psr = ARM_MODE_MON,
+ .n_indices = ARRAY_SIZE(arm_mon_indices),
+ .indices = arm_mon_indices,
},
};
return 5;
case ARMV4_5_MODE_SYS:
return 6;
+ case ARM_MODE_MON:
+ return 7;
default:
LOG_ERROR("invalid mode value encountered %d", mode);
return -1;
return ARMV4_5_MODE_UND;
case 6:
return ARMV4_5_MODE_SYS;
+ case 7:
+ return ARM_MODE_MON;
default:
LOG_ERROR("mode index out of bounds %d", number);
return ARMV4_5_MODE_ANY;
char* armv4_5_state_strings[] =
{
- "ARM", "Thumb", "Jazelle"
+ "ARM", "Thumb", "Jazelle", "ThumbEE",
};
-static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
-{
- {0, ARMV4_5_MODE_ANY, NULL, NULL},
- {1, ARMV4_5_MODE_ANY, NULL, NULL},
- {2, ARMV4_5_MODE_ANY, NULL, NULL},
- {3, ARMV4_5_MODE_ANY, NULL, NULL},
- {4, ARMV4_5_MODE_ANY, NULL, NULL},
- {5, ARMV4_5_MODE_ANY, NULL, NULL},
- {6, ARMV4_5_MODE_ANY, NULL, NULL},
- {7, ARMV4_5_MODE_ANY, NULL, NULL},
- {8, ARMV4_5_MODE_ANY, NULL, NULL},
- {9, ARMV4_5_MODE_ANY, NULL, NULL},
- {10, ARMV4_5_MODE_ANY, NULL, NULL},
- {11, ARMV4_5_MODE_ANY, NULL, NULL},
- {12, ARMV4_5_MODE_ANY, NULL, NULL},
- {13, ARMV4_5_MODE_USR, NULL, NULL},
- {14, ARMV4_5_MODE_USR, NULL, NULL},
- {15, ARMV4_5_MODE_ANY, NULL, NULL},
-
- {8, ARMV4_5_MODE_FIQ, NULL, NULL},
- {9, ARMV4_5_MODE_FIQ, NULL, NULL},
- {10, ARMV4_5_MODE_FIQ, NULL, NULL},
- {11, ARMV4_5_MODE_FIQ, NULL, NULL},
- {12, ARMV4_5_MODE_FIQ, NULL, NULL},
- {13, ARMV4_5_MODE_FIQ, NULL, NULL},
- {14, ARMV4_5_MODE_FIQ, NULL, NULL},
-
- {13, ARMV4_5_MODE_IRQ, NULL, NULL},
- {14, ARMV4_5_MODE_IRQ, NULL, NULL},
-
- {13, ARMV4_5_MODE_SVC, NULL, NULL},
- {14, ARMV4_5_MODE_SVC, NULL, NULL},
-
- {13, ARMV4_5_MODE_ABT, NULL, NULL},
- {14, ARMV4_5_MODE_ABT, NULL, NULL},
-
- {13, ARMV4_5_MODE_UND, NULL, NULL},
- {14, ARMV4_5_MODE_UND, NULL, NULL},
-
- {16, ARMV4_5_MODE_ANY, NULL, NULL},
- {16, ARMV4_5_MODE_FIQ, NULL, NULL},
- {16, ARMV4_5_MODE_IRQ, NULL, NULL},
- {16, ARMV4_5_MODE_SVC, NULL, NULL},
- {16, ARMV4_5_MODE_ABT, NULL, NULL},
- {16, ARMV4_5_MODE_UND, NULL, NULL}
+/* Templates for ARM core registers.
+ *
+ * NOTE: offsets in this table are coupled to the arm_mode_data
+ * table above, the armv4_5_core_reg_map array below, and also to
+ * the ARMV4_5_*PSR* symols.
+ */
+static const struct {
+ /* The name is used for e.g. the "regs" command. */
+ const char *name;
+
+ /* The {cookie, mode} tuple uniquely identifies one register.
+ * In a given mode, cookies 0..15 map to registers R0..R15,
+ * with R13..R15 usually called SP, LR, PC.
+ *
+ * MODE_ANY is used as *input* to the mapping, and indicates
+ * various special cases (sigh) and errors.
+ *
+ * Cookie 16 is (currently) confusing, since it indicates
+ * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
+ * (Exception modes have both CPSR and SPSR registers ...)
+ */
+ unsigned cookie;
+ enum armv4_5_mode mode;
+} arm_core_regs[] = {
+ { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
+
+ /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
+ * them as MODE_ANY creates special cases.
+ */
+ { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
+
+ /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
+ { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
+ { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+
+ { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
+
+ { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
+
+ { .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
+
+ { .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
+ { .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
+
+ { .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
+ { .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
+
+ { .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
+ { .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
+
+ { .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
+ { .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
+
+ { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
+ { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
+ { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
+ { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
+
+ { .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, },
+ { .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, },
+ { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
};
-/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
-const int armv4_5_core_reg_map[7][17] =
+/* map core mode (USR, FIQ, ...) and register number to
+ * indices into the register cache
+ */
+const int armv4_5_core_reg_map[8][17] =
{
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
- { /* FIQ */
+ { /* FIQ (8 shadows of USR, vs normal 3) */
0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
},
{ /* IRQ */
{ /* UND */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
},
- { /* SYS */
+ { /* SYS (same registers as USR) */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
+ },
+ { /* MON */
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
}
};
register_init_dummy(&arm_gdb_dummy_fps_reg);
}
-int armv4_5_get_core_reg(struct reg *reg)
+static int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
return ERROR_TARGET_NOT_HALTED;
}
- /* retval = armv4_5->armv4_5_common->full_context(target); */
retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
+ if (retval == ERROR_OK)
+ reg->valid = 1;
return retval;
}
-int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
+static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
if (target->state != TARGET_HALTED)
{
+ LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
.set = armv4_5_set_core_reg,
};
+/** Marks the contents of the register cache as invalid (and clean). */
int armv4_5_invalidate_core_regs(struct target *target)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- int i;
+ unsigned num_regs = armv4_5->core_cache->num_regs;
+ struct reg *reg = armv4_5->core_cache->reg_list;
- for (i = 0; i < 37; i++)
- {
- armv4_5->core_cache->reg_list[i].valid = 0;
- armv4_5->core_cache->reg_list[i].dirty = 0;
+ for (unsigned i = 0; i < num_regs; i++, reg++) {
+ reg->valid = 0;
+ reg->dirty = 0;
}
+ /* FIXME don't bother returning a value then */
return ERROR_OK;
}
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
{
- int num_regs = 37;
+ int num_regs = ARRAY_SIZE(arm_core_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
- struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
+ struct armv4_5_core_reg *arch_info = calloc(num_regs,
+ sizeof(struct armv4_5_core_reg));
int i;
- cache->name = "arm v4/5 registers";
+ if (!cache || !reg_list || !arch_info) {
+ free(cache);
+ free(reg_list);
+ free(arch_info);
+ return NULL;
+ }
+
+ cache->name = "ARM registers";
cache->next = NULL;
cache->reg_list = reg_list;
- cache->num_regs = num_regs;
+ cache->num_regs = 0;
- for (i = 0; i < 37; i++)
+ for (i = 0; i < num_regs; i++)
{
- arch_info[i] = armv4_5_core_reg_list_arch_info[i];
+ /* Skip registers this core doesn't expose */
+ if (arm_core_regs[i].mode == ARM_MODE_MON
+ && armv4_5_common->core_type != ARM_MODE_MON)
+ continue;
+
+ /* REVISIT handle Cortex-M, which only shadows R13/SP */
+
+ arch_info[i].num = arm_core_regs[i].cookie;
+ arch_info[i].mode = arm_core_regs[i].mode;
arch_info[i].target = target;
arch_info[i].armv4_5_common = armv4_5_common;
- reg_list[i].name = (char *) armv4_5_core_reg_list[i];
+
+ reg_list[i].name = (char *) arm_core_regs[i].name;
reg_list[i].size = 32;
- reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].value = &arch_info[i].value;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = &arch_info[i];
+
+ cache->num_regs++;
}
return cache;
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
- char output[128];
- int output_len;
- int mode, num;
struct target *target = get_current_target(CMD_CTX);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ unsigned num_regs;
+ struct reg *regs;
if (!is_arm(armv4_5))
{
if (target->state != TARGET_HALTED)
{
command_print(CMD_CTX, "error: target must be halted for register accesses");
- return ERROR_OK;
+ return ERROR_FAIL;
}
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
}
- for (num = 0; num <= 15; num++)
- {
- output_len = 0;
- for (mode = 0; mode < 6; mode++)
- {
- if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
- {
- armv4_5->full_context(target);
- }
- output_len += snprintf(output + output_len,
- 128 - output_len,
+ num_regs = armv4_5->core_cache->num_regs;
+ regs = armv4_5->core_cache->reg_list;
+
+ for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
+ const char *name;
+ char *sep = "\n";
+ char *shadow = "";
+
+ /* label this bank of registers (or shadows) */
+ switch (arm_mode_data[mode].psr) {
+ case ARMV4_5_MODE_SYS:
+ continue;
+ case ARMV4_5_MODE_USR:
+ name = "System and User";
+ sep = "";
+ break;
+ case ARM_MODE_MON:
+ if (armv4_5->core_type != ARM_MODE_MON)
+ continue;
+ /* FALLTHROUGH */
+ default:
+ name = arm_mode_data[mode].name;
+ shadow = "shadow ";
+ break;
+ }
+ command_print(CMD_CTX, "%s%s mode %sregisters",
+ sep, name, shadow);
+
+ /* display N rows of up to 4 registers each */
+ for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
+ char output[80];
+ int output_len = 0;
+
+ for (unsigned j = 0; j < 4; j++, i++) {
+ uint32_t value;
+ struct reg *reg = regs;
+
+ if (i >= arm_mode_data[mode].n_indices)
+ break;
+
+ reg += arm_mode_data[mode].indices[i];
+
+ /* REVISIT be smarter about faults... */
+ if (!reg->valid)
+ armv4_5->full_context(target);
+
+ value = buf_get_u32(reg->value, 0, 32);
+ output_len += snprintf(output + output_len,
+ sizeof(output) - output_len,
"%8s: %8.8" PRIx32 " ",
- ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
- buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
+ reg->name, value);
+ }
+ command_print(CMD_CTX, "%s", output);
}
- command_print(CMD_CTX, "%s", output);
}
- command_print(CMD_CTX,
- " cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
return ERROR_OK;
}
return ERROR_OK;
}
+static int arm_full_context(struct target *target)
+{
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ unsigned num_regs = armv4_5->core_cache->num_regs;
+ struct reg *reg = armv4_5->core_cache->reg_list;
+ int retval = ERROR_OK;
+
+ for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
+ if (reg->valid)
+ continue;
+ retval = armv4_5_get_core_reg(reg);
+ }
+ return retval;
+}
+
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
armv4_5->core_state = ARMV4_5_STATE_ARM;
armv4_5->core_mode = ARMV4_5_MODE_USR;
+ /* core_type may be overridden by subtype logic */
+ armv4_5->core_type = ARMV4_5_MODE_ANY;
+
+ /* default full_context() has no core-specific optimizations */
+ if (!armv4_5->full_context && armv4_5->read_core_reg)
+ armv4_5->full_context = arm_full_context;
+
return ERROR_OK;
}