}
};
-uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const uint8_t arm_gdb_dummy_fp_value[12];
-struct reg armv4_5_gdb_dummy_fp_reg =
+/**
+ * Dummy FPA registers are required to support GDB on ARM.
+ * Register packets require eight obsolete FPA register values.
+ * Modern ARM cores use Vector Floating Point (VFP), if they
+ * have any floating point support. VFP is not FPA-compatible.
+ */
+struct reg arm_gdb_dummy_fp_reg =
{
- .name = "GDB dummy floating-point register",
- .value = armv4_5_gdb_dummy_fp_value,
- .dirty = 0,
+ .name = "GDB dummy FPA register",
+ .value = (uint8_t *) arm_gdb_dummy_fp_value,
.valid = 1,
.size = 96,
- .arch_info = NULL,
};
-uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+static const uint8_t arm_gdb_dummy_fps_value[4];
-struct reg armv4_5_gdb_dummy_fps_reg =
+/**
+ * Dummy FPA status registers are required to support GDB on ARM.
+ * Register packets require an obsolete FPA status register.
+ */
+struct reg arm_gdb_dummy_fps_reg =
{
- .name = "GDB dummy floating-point status register",
- .value = armv4_5_gdb_dummy_fps_value,
- .dirty = 0,
+ .name = "GDB dummy FPA status register",
+ .value = (uint8_t *) arm_gdb_dummy_fps_value,
.valid = 1,
.size = 32,
- .arch_info = NULL,
};
+static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
+
+static void arm_gdb_dummy_init(void)
+{
+ register_init_dummy(&arm_gdb_dummy_fp_reg);
+ register_init_dummy(&arm_gdb_dummy_fps_reg);
+}
+
int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
cache->reg_list = reg_list;
cache->num_regs = num_regs;
- register_init_dummy(&armv4_5_gdb_dummy_fp_reg);
- register_init_dummy(&armv4_5_gdb_dummy_fps_reg);
-
for (i = 0; i < 37; i++)
{
arch_info[i] = armv4_5_core_reg_list_arch_info[i];
char output[128];
int output_len;
int mode, num;
- struct target *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(CMD_CTX);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (!is_arm(armv4_5))
{
- command_print(cmd_ctx, "current target isn't an ARM");
+ command_print(CMD_CTX, "current target isn't an ARM");
return ERROR_FAIL;
}
if (target->state != TARGET_HALTED)
{
- command_print(cmd_ctx, "error: target must be halted for register accesses");
+ command_print(CMD_CTX, "error: target must be halted for register accesses");
return ERROR_OK;
}
return ERROR_FAIL;
if (!armv4_5->full_context) {
- command_print(cmd_ctx, "error: target doesn't support %s",
+ command_print(CMD_CTX, "error: target doesn't support %s",
CMD_NAME);
return ERROR_FAIL;
}
ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
}
- command_print(cmd_ctx, "%s", output);
+ command_print(CMD_CTX, "%s", output);
}
- command_print(cmd_ctx,
+ command_print(CMD_CTX,
" cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
- struct target *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(CMD_CTX);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (!is_arm(armv4_5))
{
- command_print(cmd_ctx, "current target isn't an ARM");
+ command_print(CMD_CTX, "current target isn't an ARM");
return ERROR_FAIL;
}
}
}
- command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
+ command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
return ERROR_OK;
}
COMMAND_HANDLER(handle_armv4_5_disassemble_command)
{
int retval = ERROR_OK;
- struct target *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(CMD_CTX);
struct arm *arm = target ? target_to_arm(target) : NULL;
uint32_t address;
int count = 1;
int thumb = 0;
if (!is_arm(arm)) {
- command_print(cmd_ctx, "current target isn't an ARM");
+ command_print(CMD_CTX, "current target isn't an ARM");
return ERROR_FAIL;
}
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
- command_print(cmd_ctx, "Disassemble as Thumb");
+ command_print(CMD_CTX, "Disassemble as Thumb");
thumb = 1;
}
address &= ~1;
break;
default:
usage:
- command_print(cmd_ctx,
+ command_print(CMD_CTX,
"usage: arm disassemble <address> [<count> ['thumb']]");
count = 0;
retval = ERROR_FAIL;
if (retval != ERROR_OK)
break;
}
- command_print(cmd_ctx, "%s", cur_instruction.text);
+ command_print(CMD_CTX, "%s", cur_instruction.text);
address += cur_instruction.instruction_size;
}
for (i = 16; i < 24; i++)
{
- (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
}
- (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
return ERROR_OK;