#include "register.h"
#include "target.h"
#include "log.h"
+#include "etm.h"
typedef enum armv4_5_mode
{
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
-typedef struct armv4_5_common_s
+/* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
+#define armv4_5_common_s arm
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+typedef struct arm
{
int common_magic;
reg_cache_t *core_cache;
+
int /* armv4_5_mode */ core_mode;
enum armv4_5_state core_state;
+
+ /** Flag reporting unavailability of the BKPT instruction. */
bool is_armv4;
+
+ /** Handle for the Embedded Trace Module, if one is present. */
+ struct etm *etm;
+
int (*full_context)(struct target_s *target);
- int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
- int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
+ int (*read_core_reg)(struct target_s *target,
+ int num, enum armv4_5_mode mode);
+ int (*write_core_reg)(struct target_s *target,
+ int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
} armv4_5_common_t;
-static inline struct armv4_5_common_s *
-target_to_armv4_5(struct target_s *target)
+#define target_to_armv4_5 target_to_arm
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target_s *target)
{
return target->arch_info;
}
-typedef struct armv4_5_algorithm_s
+static inline bool is_arm(struct arm *arm)
+{
+ return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+}
+
+struct armv4_5_algorithm
{
int common_magic;
enum armv4_5_mode core_mode;
enum armv4_5_state core_state;
-} armv4_5_algorithm_t;
+};
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
{
int num;
enum armv4_5_mode mode;
target_t *target;
armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+};
reg_cache_t* armv4_5_build_reg_cache(target_t *target,
armv4_5_common_t *armv4_5_common);
int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
int armv4_5_run_algorithm(struct target_s *target,
- int num_mem_params, mem_param_t *mem_params,
- int num_reg_params, reg_param_t *reg_params,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);