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ARM: remove per-register malloc
[openocd.git] / src / target / armv4_5.h
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 3c8411f04100488516b2c17b12540cd8c38e83b5..50af57b36c716313acd786750a90c3da50bac494 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -5,6 +5,9 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
+ *   Copyright (C) 2009 by Øyvind Harboe                                   *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -23,9 +26,7 @@
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
-#include "register.h"
 #include "target.h"
-#include "log.h"
 
 typedef enum armv4_5_mode
 {
@@ -34,28 +35,32 @@ typedef enum armv4_5_mode
        ARMV4_5_MODE_IRQ = 18,
        ARMV4_5_MODE_SVC = 19,
        ARMV4_5_MODE_ABT = 23,
+       ARM_MODE_MON = 26,
        ARMV4_5_MODE_UND = 27,
        ARMV4_5_MODE_SYS = 31,
        ARMV4_5_MODE_ANY = -1
 } armv4_5_mode_t;
 
-extern char** armv4_5_mode_strings;
+const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
+int armv4_5_mode_to_number(enum armv4_5_mode mode);
+enum armv4_5_mode armv4_5_number_to_mode(int number);
 
 typedef enum armv4_5_state
 {
        ARMV4_5_STATE_ARM,
        ARMV4_5_STATE_THUMB,
        ARMV4_5_STATE_JAZELLE,
+       ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
-extern int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
                cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
-               cache->reg_list[armv4_5_core_reg_map[mode][num]]
 
 /* offsets into armv4_5 core register cache */
 enum
@@ -65,88 +70,107 @@ enum
        ARMV4_5_SPSR_IRQ = 33,
        ARMV4_5_SPSR_SVC = 34,
        ARMV4_5_SPSR_ABT = 35,
-       ARMV4_5_SPSR_UND = 36
+       ARMV4_5_SPSR_UND = 36,
+       ARM_SPSR_MON = 39,
 };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-typedef struct armv4_5_common_s
+/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
+#define armv4_5_common_s arm
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+struct arm
 {
        int common_magic;
-       reg_cache_t *core_cache;
+       struct reg_cache *core_cache;
+
+       /**
+        * Indicates what registers are in the ARM state core register set.
+        * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+        * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+        * more registers are shadowed, for "Secure Monitor" mode.
+        */
+       enum armv4_5_mode core_type;
+
        enum armv4_5_mode core_mode;
        enum armv4_5_state core_state;
+
+       /** Flag reporting unavailability of the BKPT instruction. */
        bool is_armv4;
-       int (*full_context)(struct target_s *target);
-       int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
-       int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
+
+       /** Handle for the Embedded Trace Module, if one is present. */
+       struct etm_context *etm;
+
+       int (*full_context)(struct target *target);
+       int (*read_core_reg)(struct target *target,
+                       int num, enum armv4_5_mode mode);
+       int (*write_core_reg)(struct target *target,
+                       int num, enum armv4_5_mode mode, uint32_t value);
        void *arch_info;
-} armv4_5_common_t;
+};
+
+#define target_to_armv4_5 target_to_arm
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target *target)
+{
+       return target->arch_info;
+}
 
-typedef struct armv4_5_algorithm_s
+static inline bool is_arm(struct arm *arm)
+{
+       return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+}
+
+struct armv4_5_algorithm
 {
        int common_magic;
 
        enum armv4_5_mode core_mode;
        enum armv4_5_state core_state;
-} armv4_5_algorithm_t;
+};
 
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
 {
        int num;
        enum armv4_5_mode mode;
-       target_t *target;
-       armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+       struct target *target;
+       struct arm *armv4_5_common;
+       uint32_t value;
+};
 
-extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
+struct reg_cache* armv4_5_build_reg_cache(struct target *target,
+               struct arm *armv4_5_common);
 
-/* map psr mode bits to linear number */
-static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
-{
-       switch (mode)
-       {
-               case ARMV4_5_MODE_USR: return 0; break;
-               case ARMV4_5_MODE_FIQ: return 1; break;
-               case ARMV4_5_MODE_IRQ: return 2; break;
-               case ARMV4_5_MODE_SVC: return 3; break;
-               case ARMV4_5_MODE_ABT: return 4; break;
-               case ARMV4_5_MODE_UND: return 5; break;
-               case ARMV4_5_MODE_SYS: return 6; break;
-               case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
-               default:
-                       LOG_ERROR("invalid mode value encountered %d", mode);
-                       return -1;
-       }
-}
+int armv4_5_arch_state(struct target *target);
+int armv4_5_get_gdb_reg_list(struct target *target,
+               struct reg **reg_list[], int *reg_list_size);
 
-/* map linear number to mode bits */
-static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
-{
-       switch (number)
-       {
-               case 0: return ARMV4_5_MODE_USR; break;
-               case 1: return ARMV4_5_MODE_FIQ; break;
-               case 2: return ARMV4_5_MODE_IRQ; break;
-               case 3: return ARMV4_5_MODE_SVC; break;
-               case 4: return ARMV4_5_MODE_ABT; break;
-               case 5: return ARMV4_5_MODE_UND; break;
-               case 6: return ARMV4_5_MODE_SYS; break;
-               default:
-                       LOG_ERROR("mode index out of bounds %d", number);
-                       return ARMV4_5_MODE_ANY;
-       }
-};
+int armv4_5_register_commands(struct command_context *cmd_ctx);
+int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 
-extern int armv4_5_arch_state(struct target_s *target);
-extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
+int armv4_5_run_algorithm(struct target *target,
+               int num_mem_params, struct mem_param *mem_params,
+               int num_reg_params, struct reg_param *reg_params,
+               uint32_t entry_point, uint32_t exit_point,
+               int timeout_ms, void *arch_info);
 
-extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_invalidate_core_regs(struct target *target);
 
-extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
+int arm_checksum_memory(struct target *target,
+               uint32_t address, uint32_t count, uint32_t *checksum);
+int arm_blank_check_memory(struct target *target,
+               uint32_t address, uint32_t count, uint32_t *blank);
 
-extern int armv4_5_invalidate_core_regs(target_t *target);
+extern struct reg arm_gdb_dummy_fp_reg;
+extern struct reg arm_gdb_dummy_fps_reg;
 
 /* ARM mode instructions
  */
@@ -315,4 +339,16 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  */
 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 
+/* build basic mrc/mcr opcode */
+
+static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+       uint32_t t = 0;
+       t|=op1<<21;
+       t|=op2<<5;
+       t|=CRn<<16;
+       t|=CRm<<0;
+       return t;
+}
+
 #endif /* ARMV4_5_H */
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