ARMV4_5_STATE_ARM,
ARMV4_5_STATE_THUMB,
ARMV4_5_STATE_JAZELLE,
+ ARM_STATE_THUMB_EE,
} armv4_5_state_t;
extern char* armv4_5_state_strings[];
-extern const int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
ARMV4_5_SPSR_IRQ = 33,
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
- ARMV4_5_SPSR_UND = 36
+ ARMV4_5_SPSR_UND = 36,
+ ARM_SPSR_MON = 39,
};
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
int common_magic;
struct reg_cache *core_cache;
- int /* armv4_5_mode */ core_mode;
+ /**
+ * Indicates what registers are in the ARM state core register set.
+ * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+ * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
+ * more registers are shadowed, for "Secure Monitor" mode.
+ */
+ enum armv4_5_mode core_type;
+
+ enum armv4_5_mode core_mode;
enum armv4_5_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
enum armv4_5_mode mode;
struct target *target;
struct arm *armv4_5_common;
+ uint32_t value;
};
struct reg_cache* armv4_5_build_reg_cache(struct target *target,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
-int armv4_5_invalidate_core_regs(struct target *target);
-
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,