+ // FIXME not supported present in cortex A8 and later
+ // in cortex A7, A15
+ LOG_ERROR("cache l2 present :not supported");
+ }
+ /* retrieve selected cache */
+ /* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ &cache_selected);
+ if (retval!=ERROR_OK) goto done;
+
+ retval = armv7a->armv4_5_common.mrc(target, 15,
+ 2, 0, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ &cache_selected);
+ /* select instruction cache*/
+ /* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */
+ /* [0] : 1 instruction cache selection , 0 data cache selection */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ 1);
+ if (retval!=ERROR_OK) goto done;
+
+ /* read CCSIDR*/
+ /* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR */
+ /* [2:0] line size 001 eight word per line */
+ /* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ &cache_i_reg);
+ if (retval!=ERROR_OK) goto done;
+
+ /* select data cache*/
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ 0);
+ if (retval!=ERROR_OK) goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ &cache_d_reg);
+ if (retval!=ERROR_OK) goto done;
+
+ /* restore selected cache */
+ dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ cache_selected);
+
+ if (retval != ERROR_OK) goto done;
+ dpm->finish(dpm);
+
+ // put fake type
+ cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
+ cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
+ cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
+ cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) +1;
+ /* compute info for set way operation on cache */
+ cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
+ cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
+ cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
+ cache->d_u_size.way_shift = cache->d_u_size.way+1;