Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / armv7a.c
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 2be70b78b04c7d95553944b64aea9b5a67c079be..82f4be5a0b98718ac27536c4069be28ebe557b0d 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /***************************************************************************
  *    Copyright (C) 2009 by David Brownell                                 *
  *                                                                         *
  *    Copyright (C) ST-Ericsson SA 2011 michel.jaouen@stericsson.com       *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -38,6 +27,7 @@
 #include "arm_opcodes.h"
 #include "target.h"
 #include "target_type.h"
+#include "smp.h"
 
 static void armv7a_show_fault_registers(struct target *target)
 {
@@ -50,7 +40,7 @@ static void armv7a_show_fault_registers(struct target *target)
        if (retval != ERROR_OK)
                return;
 
-       /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+       /* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
 
        /* c5/c0 - {data, instruction} fault status registers */
        retval = dpm->instr_read_data_r0(dpm,
@@ -111,7 +101,7 @@ static int armv7a_read_midr(struct target *target)
        armv7a->arch = (midr >> 16) & 0xf;
        armv7a->variant = (midr >> 20) & 0xf;
        armv7a->implementor = (midr >> 24) & 0xff;
-       LOG_INFO("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
+       LOG_DEBUG("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
                         ", variant %" PRIx32 ", implementor %" PRIx32,
                 target->cmd_name,
                 armv7a->rev,
@@ -160,7 +150,7 @@ int armv7a_read_ttbcr(struct target *target)
        }
 
        /*
-        * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+        * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
         * document # ARM DDI 0406C
         */
        armv7a->armv7a_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
@@ -193,8 +183,7 @@ done:
 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
 {
        struct armv7a_l2x_cache *l2x_cache;
-       struct target_list *head = target->head;
-       struct target *curr;
+       struct target_list *head;
 
        struct armv7a_common *armv7a = target_to_armv7a(target);
        l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
@@ -207,15 +196,14 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
        armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
        /*  initialize all target in this cluster (smp target)
         *  l2 cache must be configured after smp declaration */
-       while (head != (struct target_list *)NULL) {
-               curr = head->target;
+       foreach_smp_target(head, target->smp_targets) {
+               struct target *curr = head->target;
                if (curr != target) {
                        armv7a = target_to_armv7a(curr);
                        if (armv7a->armv7a_mmu.armv7a_cache.outer_cache)
                                LOG_ERROR("smp target : outer cache already initialized\n");
                        armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
                }
-               head = head->next;
        }
        return JIM_OK;
 }
@@ -257,10 +245,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 
                if (arch->ctype & 1) {
                        command_print(cmd,
-                               "L%d I-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
+                               "L%d I-Cache: linelen %" PRIu32
+                               ", associativity %" PRIu32
+                               ", nsets %" PRIu32
+                               ", cachesize %" PRIu32 " KBytes",
                                cl+1,
                                arch->i_size.linelen,
                                arch->i_size.associativity,
@@ -270,10 +258,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 
                if (arch->ctype >= 2) {
                        command_print(cmd,
-                               "L%d D-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
+                               "L%d D-Cache: linelen %" PRIu32
+                               ", associativity %" PRIu32
+                               ", nsets %" PRIu32
+                               ", cachesize %" PRIu32 " KBytes",
                                cl+1,
                                arch->d_u_size.linelen,
                                arch->d_u_size.associativity,
@@ -282,8 +270,8 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
                }
        }
 
-       if (l2x_cache != NULL)
-               command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
+       if (l2x_cache)
+               command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
                        l2x_cache->base, l2x_cache->way);
 
        return ERROR_OK;
@@ -399,7 +387,7 @@ int armv7a_identify_cache(struct target *target)
 
        cache->iminline = 4UL << (ctr & 0xf);
        cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
                 ctr, cache->iminline, cache->dminline);
 
        /*  retrieve CLIDR
@@ -439,13 +427,13 @@ int armv7a_identify_cache(struct target *target)
                                goto done;
                        cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+                       LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].d_u_size.index,
                                        cache->arch[cl].d_u_size.index_shift,
                                        cache->arch[cl].d_u_size.way,
                                        cache->arch[cl].d_u_size.way_shift);
 
-                       LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].d_u_size.linelen,
                                        cache->arch[cl].d_u_size.cachesize,
                                        cache->arch[cl].d_u_size.associativity);
@@ -459,13 +447,13 @@ int armv7a_identify_cache(struct target *target)
                                goto done;
                        cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+                       LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].i_size.index,
                                        cache->arch[cl].i_size.index_shift,
                                        cache->arch[cl].i_size.way,
                                        cache->arch[cl].i_size.way_shift);
 
-                       LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].i_size.linelen,
                                        cache->arch[cl].i_size.cachesize,
                                        cache->arch[cl].i_size.associativity);
@@ -483,7 +471,7 @@ int armv7a_identify_cache(struct target *target)
                goto done;
 
        /*  if no l2 cache initialize l1 data cache flush function function */
-       if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) {
+       if (!armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) {
                armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
                        armv7a_cache_auto_flush_all_data;
        }
@@ -570,9 +558,6 @@ int armv7a_arch_state(struct target *target)
 
        if (arm->core_mode == ARM_MODE_ABT)
                armv7a_show_fault_registers(target);
-       if (target->debug_reason == DBG_REASON_WATCHPOINT)
-               LOG_USER("Watchpoint triggered at PC %#08x",
-                       (unsigned) armv7a->dpm.wp_pc);
 
        return ERROR_OK;
 }
@@ -589,7 +574,7 @@ static const struct command_registration l2_cache_commands[] = {
 
 };
 
-const struct command_registration l2x_cache_command_handlers[] = {
+static const struct command_registration l2x_cache_command_handlers[] = {
        {
                .name = "cache_config",
                .mode = COMMAND_EXEC,
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)