-static int armv7a_flush_all_data( struct target * target)
-{
- int retval = ERROR_FAIL;
- /* check that armv7a_cache is correctly identify */
- struct armv7a_common *armv7a = target_to_armv7a(target);
- if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1)
- {
- LOG_ERROR("trying to flush un-identified cache");
- return retval;
- }
-
- if (target->smp)
- {
- /* look if all the other target have been flushed in order to flush level
- * 2 */
- struct target_list *head;
- struct target *curr;
- head = target->head;
- while(head != (struct target_list*)NULL)
- {
- curr = head->target;
- if ((curr->state == TARGET_HALTED))
- { LOG_INFO("Wait flushing data l1 on core %d",curr->coreid);
- retval = _armv7a_flush_all_data(curr);
- }
- head = head->next;
- }
- }
- else retval = _armv7a_flush_all_data(target);
- return retval;
-}
-
-
-/* L2 is not specific to armv7a a specific file is needed */
-static int armv7a_l2x_flush_all_data(struct target * target)
-{
-
-#define L2X0_CLEAN_INV_WAY 0x7FC
- int retval = ERROR_FAIL;
- struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache*)
- (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
- uint32_t base = l2x_cache->base;
- uint32_t l2_way = l2x_cache->way;
- uint32_t l2_way_val = (1<<l2_way) -1;
- retval = armv7a_flush_all_data(target);
- if (retval!=ERROR_OK) return retval;
- retval = target->type->write_phys_memory(target,
- (uint32_t)(base+(uint32_t)L2X0_CLEAN_INV_WAY),
- (uint32_t)4,
- (uint32_t)1,
- (uint8_t*)&l2_way_val);
- return retval;
-}
-
-static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
- struct armv7a_cache_common *armv7a_cache)
-{
-
- struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache*)
- (armv7a_cache->l2_cache);
-
- if (armv7a_cache->ctype == -1)
- {
- command_print(cmd_ctx, "cache not yet identified");
- return ERROR_OK;
- }
-
- command_print(cmd_ctx,
- "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
- armv7a_cache->d_u_size.linelen,
- armv7a_cache->d_u_size.associativity,
- armv7a_cache->d_u_size.nsets,
- armv7a_cache->d_u_size.cachesize);
-
- command_print(cmd_ctx,
- "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
- armv7a_cache->i_size.linelen,
- armv7a_cache->i_size.associativity,
- armv7a_cache->i_size.nsets,
- armv7a_cache->i_size.cachesize);
- command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways",
- l2x_cache->base, l2x_cache->way);
-
-
- return ERROR_OK;
-}
-
-