+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, 0),
+ &ttbr0);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, 1),
+ &ttbr1);
+ if (retval != ERROR_OK)
+ goto done;
+
+ LOG_INFO("ttbcr %" PRIx32 "ttbr0 %" PRIx32 "ttbr1 %" PRIx32, ttbcr, ttbr0, ttbr1);
+
+ armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
+ armv7a->armv7a_mmu.ttbr0_mask = 0;
+
+ retval = armv7a_read_midr(target);
+ if (retval != ERROR_OK)
+ goto done;
+
+ if (armv7a->partnum & 0xf) {
+ /*
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * document # ARM DDI 0406C
+ */
+ armv7a->armv7a_mmu.ttbr0_mask = 1 << (14 - ((ttbcr & 0x7)));
+ } else {
+ /* ARM DDI 0344H , ARM DDI 0407F */
+ armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
+ /* fix me , default is hard coded LINUX border */
+ armv7a->armv7a_mmu.os_border = 0xc0000000;
+ }
+
+ LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32,
+ armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
+ armv7a->armv7a_mmu.ttbr0_mask);
+
+ if (armv7a->armv7a_mmu.ttbr1_used == 1) {
+ LOG_INFO("SVC access above %" PRIx32,
+ (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
+ armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
+ }
+done:
+ dpm->finish(dpm);
+ return retval;
+}
+
+/* method adapted to cortex A : reused arm v4 v5 method*/
+int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
+{
+ uint32_t first_lvl_descriptor = 0x0;
+ uint32_t second_lvl_descriptor = 0x0;
+ int retval;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm_dpm *dpm = armv7a->arm.dpm;
+ uint32_t ttb = 0; /* default ttb0 */
+ if (armv7a->armv7a_mmu.ttbr1_used == -1)
+ armv7a_read_ttbcr(target);
+ if ((armv7a->armv7a_mmu.ttbr1_used) &&
+ (va > (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask))) {
+ /* select ttb 1 */
+ ttb = 1;
+ }
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* MRC p15,0,<Rt>,c2,c0,ttb */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
+ &ttb);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = armv7a->armv7a_mmu.read_physical_memory(target,
+ (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
+ 4, 1, (uint8_t *)&first_lvl_descriptor);
+ if (retval != ERROR_OK)
+ return retval;
+ first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
+ &first_lvl_descriptor);
+ /* reuse armv4_5 piece of code, specific armv7a changes may come later */
+ LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
+
+ if ((first_lvl_descriptor & 0x3) == 0) {
+ LOG_ERROR("Address translation failure");
+ return ERROR_TARGET_TRANSLATION_FAULT;
+ }
+
+
+ if ((first_lvl_descriptor & 0x3) == 2) {
+ /* section descriptor */
+ *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
+ return ERROR_OK;
+ }
+
+ if ((first_lvl_descriptor & 0x3) == 1) {
+ /* coarse page table */
+ retval = armv7a->armv7a_mmu.read_physical_memory(target,
+ (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
+ 4, 1, (uint8_t *)&second_lvl_descriptor);
+ if (retval != ERROR_OK)
+ return retval;
+ } else if ((first_lvl_descriptor & 0x3) == 3) {
+ /* fine page table */
+ retval = armv7a->armv7a_mmu.read_physical_memory(target,
+ (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
+ 4, 1, (uint8_t *)&second_lvl_descriptor);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
+ &second_lvl_descriptor);
+
+ LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
+
+ if ((second_lvl_descriptor & 0x3) == 0) {
+ LOG_ERROR("Address translation failure");
+ return ERROR_TARGET_TRANSLATION_FAULT;
+ }
+
+ if ((second_lvl_descriptor & 0x3) == 1) {
+ /* large page descriptor */
+ *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
+ return ERROR_OK;
+ }
+
+ if ((second_lvl_descriptor & 0x3) == 2) {
+ /* small page descriptor */
+ *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
+ return ERROR_OK;
+ }
+
+ if ((second_lvl_descriptor & 0x3) == 3) {
+ *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
+ return ERROR_OK;
+ }
+
+ /* should not happen */
+ LOG_ERROR("Address translation failure");
+ return ERROR_TARGET_TRANSLATION_FAULT;
+
+done:
+ return retval;
+}
+
+/* V7 method VA TO PA */
+int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
+ uint32_t *val, int meminfo)
+{
+ int retval = ERROR_FAIL;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm_dpm *dpm = armv7a->arm.dpm;
+ uint32_t virt = va & ~0xfff;
+ uint32_t NOS, NS, INNER, OUTER;
+ *val = 0xdeadbeef;
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+ /* mmu must be enable in order to get a correct translation
+ * use VA to PA CP15 register for conversion */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 0, 0, 7, 8, 0),
+ virt);
+ if (retval != ERROR_OK)
+ goto done;
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
+ val);
+ /* decode memory attribute */
+ NOS = (*val >> 10) & 1; /* Not Outer shareable */
+ NS = (*val >> 9) & 1; /* Non secure */
+ INNER = (*val >> 4) & 0x7;
+ OUTER = (*val >> 2) & 0x3;
+
+ if (retval != ERROR_OK)
+ goto done;
+ *val = (*val & ~0xfff) + (va & 0xfff);
+ if (*val == va)
+ LOG_WARNING("virt = phys : MMU disable !!");
+ if (meminfo) {
+ LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured",
+ va, *val,
+ NOS == 1 ? "not" : " ",
+ NS == 1 ? "not" : "");
+ switch (OUTER) {
+ case 0:
+ LOG_INFO("outer: Non-Cacheable");
+ break;
+ case 1:
+ LOG_INFO("outer: Write-Back, Write-Allocate");
+ break;
+ case 2:
+ LOG_INFO("outer: Write-Through, No Write-Allocate");
+ break;
+ case 3:
+ LOG_INFO("outer: Write-Back, no Write-Allocate");
+ break;
+ }
+ switch (INNER) {
+ case 0:
+ LOG_INFO("inner: Non-Cacheable");
+ break;
+ case 1:
+ LOG_INFO("inner: Strongly-ordered");
+ break;
+ case 3:
+ LOG_INFO("inner: Device");
+ break;
+ case 5:
+ LOG_INFO("inner: Write-Back, Write-Allocate");
+ break;
+ case 6:
+ LOG_INFO("inner: Write-Through");
+ break;
+ case 7:
+ LOG_INFO("inner: Write-Back, no Write-Allocate");
+
+ default:
+ LOG_INFO("inner: %" PRIx32 " ???", INNER);
+ }
+ }
+
+done:
+ dpm->finish(dpm);
+
+ return retval;
+}
+
+static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx,
+ struct armv7a_cache_common *armv7a_cache)
+{
+ if (armv7a_cache->ctype == -1) {
+ command_print(cmd_ctx, "cache not yet identified");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx,
+ "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
+ armv7a_cache->d_u_size.linelen,
+ armv7a_cache->d_u_size.associativity,
+ armv7a_cache->d_u_size.nsets,
+ armv7a_cache->d_u_size.cachesize);
+
+ command_print(cmd_ctx,
+ "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
+ armv7a_cache->i_size.linelen,
+ armv7a_cache->i_size.associativity,
+ armv7a_cache->i_size.nsets,
+ armv7a_cache->i_size.cachesize);