armv7a: fix scan-build warnings

[openocd.git] / src / target / armv7a.c

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index e0d08827f62a730eed52eef462efac54fcb5292e..67c563e67e17bf202174e9888d4045cce76dd26d 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -87,7 +87,7 @@ done:
        /* (void) */ dpm->finish(dpm);
 }
 
-int armv7a_read_ttbcr(struct target *target)
+static int armv7a_read_ttbcr(struct target *target)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
@@ -129,7 +129,6 @@ int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
        uint32_t first_lvl_descriptor = 0x0;
        uint32_t second_lvl_descriptor = 0x0;
        int retval;
-       uint32_t cb;
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
        uint32_t ttb = 0; /*  default ttb0 */
@@ -148,6 +147,8 @@ int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
        retval = dpm->instr_read_data_r0(dpm,
                        ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
                        &ttb);
+       if (retval != ERROR_OK)
+               return retval;
        retval = armv7a->armv7a_mmu.read_physical_memory(target,
                        (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
                        4, 1, (uint8_t*)&first_lvl_descriptor);
@@ -168,7 +169,6 @@ int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
        if ((first_lvl_descriptor & 0x3) == 2)
        {
                /* section descriptor */
-               cb = (first_lvl_descriptor & 0xc) >> 2;
                *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
                return ERROR_OK;
        }
@@ -203,9 +203,6 @@ int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
                return ERROR_TARGET_TRANSLATION_FAULT;
        }
 
-       /* cacheable/bufferable is always specified in bits 3-2 */
-       cb = (second_lvl_descriptor & 0xc) >> 2;
-
        if ((second_lvl_descriptor & 0x3) == 1)
        {
                /* large page descriptor */
@@ -243,7 +240,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
        uint32_t virt = va & ~0xfff;
-       uint32_t NOS,NS,SH,INNER,OUTER;
+       uint32_t NOS,NS,INNER,OUTER;
        *val = 0xdeadbeef;
        retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
@@ -260,7 +257,6 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
        /* decode memory attribute */
        NOS = (*val >> 10) & 1; /*  Not Outer shareable */
        NS = (*val >> 9) & 1; /* Non secure */
-       SH = (*val >> 7 )& 1; /*  shareable */
        INNER = (*val >> 4) &  0x7;
        OUTER = (*val >> 2) & 0x3;
 
@@ -460,15 +456,13 @@ static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
 }
 
 
-int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
+static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
 {
        struct armv7a_l2x_cache *l2x_cache;
        struct target_list *head = target->head;
        struct target *curr;
 
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       if (armv7a == NULL)
-               LOG_ERROR("not an armv7a target");
        l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
        l2x_cache->base = base;
        l2x_cache->way = way;
@@ -548,7 +542,7 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 
 
 /*  retrieve core id cluster id  */
-int arnv7a_read_mpidr(struct target *target)
+static int armv7a_read_mpidr(struct target *target)
 {
     int retval = ERROR_FAIL;
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -622,6 +616,7 @@ int armv7a_identify_cache(struct target *target)
                        2, 0,   /* op1, op2 */
                        0, 0,   /* CRn, CRm */
                        &cache_selected);
+       if (retval!=ERROR_OK) goto done;
        /* select instruction cache*/
        /*  MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */
        /*  [0]  : 1 instruction cache selection , 0 data cache selection */
@@ -717,7 +712,7 @@ int armv7a_identify_cache(struct target *target)
 
 done:
        dpm->finish(dpm);
-        arnv7a_read_mpidr(target);
+       armv7a_read_mpidr(target);
        return retval;
 
 }
@@ -726,7 +721,6 @@ done:
 
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 {
-       struct armv7a_common *again;
        struct arm *armv4_5 = &armv7a->armv4_5_common;
     armv4_5->arch_info = armv7a;
        target->arch_info = &armv7a->armv4_5_common;
@@ -738,7 +732,6 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
        armv7a->armv7a_mmu.armv7a_cache.ctype = -1;
        armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
     armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
-    again =target_to_armv7a(target);
        return ERROR_OK;
 }