Fix spelling of ARM Cortex

[openocd.git] / src / target / armv7a.c

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 18416e5a94ab0527e5d0b49eeab8c28b781506dd..6dbe10d74139dceff9a2d17606cbd97c1fc1e850 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -172,19 +172,12 @@ static int armv7a_read_ttbcr(struct target *target)
                  armv7a->armv7a_mmu.ttbr_mask[0],
                  armv7a->armv7a_mmu.ttbr_mask[1]);
 
-       /* FIXME: default is hard coded LINUX border  */
-       armv7a->armv7a_mmu.os_border = 0xc0000000;
-       if (ttbcr_n != 0) {
-               LOG_INFO("SVC access above %" PRIx32,
-                       armv7a->armv7a_mmu.ttbr_range[0] + 1);
-               armv7a->armv7a_mmu.os_border = armv7a->armv7a_mmu.ttbr_range[0] + 1;
-       }
 done:
        dpm->finish(dpm);
        return retval;
 }
 
-/*  method adapted to cortex A : reused arm v4 v5 method*/
+/*  method adapted to Cortex-A : reused ARM v4 v5 method */
 int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
 {
        uint32_t first_lvl_descriptor = 0x0;
@@ -376,49 +369,6 @@ done:
        return retval;
 }
 
-static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx,
-       struct armv7a_cache_common *armv7a_cache)
-{
-       int cl;
-
-       if (armv7a_cache->info == -1) {
-               command_print(cmd_ctx, "cache not yet identified");
-               return ERROR_OK;
-       }
-
-       for (cl = 0; cl < armv7a_cache->loc; cl++) {
-               struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
-
-               if (arch->ctype & 1) {
-                       command_print(cmd_ctx,
-                               "L%d I-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
-                               cl+1,
-                               arch->i_size.linelen,
-                               arch->i_size.associativity,
-                               arch->i_size.nsets,
-                               arch->i_size.cachesize);
-               }
-
-               if (arch->ctype >= 2) {
-                       command_print(cmd_ctx,
-                               "L%d D-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
-                               cl+1,
-                               arch->d_u_size.linelen,
-                               arch->d_u_size.associativity,
-                               arch->d_u_size.nsets,
-                               arch->d_u_size.cachesize);
-               }
-       }
-
-       return ERROR_OK;
-}
-
 /* FIXME: remove it */
 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
 {
@@ -475,13 +425,43 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
        struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
                (armv7a_cache->outer_cache);
 
+       int cl;
+
        if (armv7a_cache->info == -1) {
                command_print(cmd_ctx, "cache not yet identified");
                return ERROR_OK;
        }
 
-       if (armv7a_cache->display_cache_info)
-               armv7a_cache->display_cache_info(cmd_ctx, armv7a_cache);
+       for (cl = 0; cl < armv7a_cache->loc; cl++) {
+               struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
+
+               if (arch->ctype & 1) {
+                       command_print(cmd_ctx,
+                               "L%d I-Cache: linelen %" PRIi32
+                               ", associativity %" PRIi32
+                               ", nsets %" PRIi32
+                               ", cachesize %" PRId32 " KBytes",
+                               cl+1,
+                               arch->i_size.linelen,
+                               arch->i_size.associativity,
+                               arch->i_size.nsets,
+                               arch->i_size.cachesize);
+               }
+
+               if (arch->ctype >= 2) {
+                       command_print(cmd_ctx,
+                               "L%d D-Cache: linelen %" PRIi32
+                               ", associativity %" PRIi32
+                               ", nsets %" PRIi32
+                               ", cachesize %" PRId32 " KBytes",
+                               cl+1,
+                               arch->d_u_size.linelen,
+                               arch->d_u_size.associativity,
+                               arch->d_u_size.nsets,
+                               arch->d_u_size.cachesize);
+               }
+       }
+
        if (l2x_cache != NULL)
                command_print(cmd_ctx, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
                        l2x_cache->base, l2x_cache->way);
@@ -689,8 +669,6 @@ int armv7a_identify_cache(struct target *target)
 
        /*  if no l2 cache initialize l1 data cache flush function function */
        if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) {
-               armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
-                       armv7a_handle_inner_cache_info_command;
                armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
                        armv7a_cache_auto_flush_all_data;
        }
@@ -715,7 +693,6 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
        armv7a->armv7a_mmu.armv7a_cache.info = -1;
        armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
        armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
-       armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
        armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1;
        return ERROR_OK;
 }