l2x_cache->base,l2x_cache->way);*/
if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
LOG_INFO("cache l2 already initialized\n");
- armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache;
+ armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
/* initialize l1 / l2x cache function */
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache
= armv7a_l2x_flush_all_data;
armv7a = target_to_armv7a(curr);
if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
LOG_ERROR("smp target : cache l2 already initialized\n");
- armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache;
+ armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
armv7a_l2x_flush_all_data;
armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
&mpidr);
if (retval != ERROR_OK)
goto done;
+
+ /* ARMv7R uses a different format for MPIDR.
+ * When configured uniprocessor (most R cores) it reads as 0.
+ * This will need to be implemented for multiprocessor ARMv7R cores. */
+ if (armv7a->is_armv7r) {
+ if (mpidr)
+ LOG_ERROR("MPIDR nonzero in ARMv7-R target");
+ goto done;
+ }
+
if (mpidr & 1<<31) {
armv7a->multi_processor_system = (mpidr >> 30) & 1;
armv7a->cluster_id = (mpidr >> 8) & 0xf;
armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
} else
- LOG_ERROR("mpdir not in multiprocessor format");
+ LOG_ERROR("MPIDR not in multiprocessor format");
done:
dpm->finish(dpm);
{
.name = "cache_config",
.mode = COMMAND_EXEC,
- .help = "cache configuation for a target",
+ .help = "cache configuration for a target",
.usage = "",
.chain = l2_cache_commands,
},