armv7a: cache ttbcr and ttb0/1 on debug state entry

[openocd.git] / src / target / armv7a.h

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 6a62f72c6cc0240d0cf85540e3988c479d123592..33f6f5dbea15c75aa23a110e7b9e8d5689db6e7d 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -48,7 +48,6 @@ struct armv7a_l2x_cache {
 };
 
 struct armv7a_cachesize {
-       uint32_t level_num;
        /*  cache dimensionning */
        uint32_t linelen;
        uint32_t associativity;
@@ -88,10 +87,11 @@ struct armv7a_mmu_common {
        /* following field mmu working way */
        int32_t cached;     /* 0: not initialized, 1: initialized */
        uint32_t ttbcr;     /* cache for ttbcr register */
+       uint32_t ttbr[2];
        uint32_t ttbr_mask[2];
        uint32_t ttbr_range[2];
 
-       int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
+       int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
                        uint32_t count, uint8_t *buffer);
        struct armv7a_cache_common armv7a_cache;
        uint32_t mmu_enabled;