* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef ARMV7A_H
-#define ARMV7A_H
-#include "register.h"
-#include "target.h"
-#include "log.h"
+#ifndef OPENOCD_TARGET_ARMV7A_H
+#define OPENOCD_TARGET_ARMV7A_H
+
#include "arm_adi_v5.h"
-#include "armv4_5.h"
+#include "armv7a_cache.h"
+#include "arm.h"
#include "armv4_5_mmu.h"
#include "armv4_5_cache.h"
+#include "arm_dpm.h"
-typedef enum armv7a_mode
-{
- ARMV7A_MODE_USR = 16,
- ARMV7A_MODE_FIQ = 17,
- ARMV7A_MODE_IRQ = 18,
- ARMV7A_MODE_SVC = 19,
- ARMV7A_MODE_ABT = 23,
- ARMV7A_MODE_UND = 27,
- ARMV7A_MODE_SYS = 31,
- ARMV7A_MODE_MON = 22,
- ARMV7A_MODE_ANY = -1
-} armv7a_t;
-
-extern char **armv7a_mode_strings;
-
-typedef enum armv7a_state
-{
- ARMV7A_STATE_ARM,
- ARMV7A_STATE_THUMB,
- ARMV7A_STATE_JAZELLE,
- ARMV7A_STATE_THUMBEE,
-} armv7a_state_t;
+enum {
+ ARM_PC = 15,
+ ARM_CPSR = 16
+};
-extern char *armv7a_state_strings[];
+#define ARMV7_COMMON_MAGIC 0x0A450999
-extern int armv7a_core_reg_map[8][17];
+/* VA to PA translation operations opc2 values*/
+#define V2PCWPR 0
+#define V2PCWPW 1
+#define V2PCWUR 2
+#define V2PCWUW 3
+#define V2POWPR 4
+#define V2POWPW 5
+#define V2POWUR 6
+#define V2POWUW 7
+/* L210/L220 cache controller support */
+struct armv7a_l2x_cache {
+ uint32_t base;
+ uint32_t way;
+};
-#define ARMV7A_CORE_REG_MODE(cache, mode, num) \
- cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
-#define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
- cache->reg_list[armv7a_core_reg_map[mode][num]]
+struct armv7a_cachesize {
+ /* cache dimensionning */
+ uint32_t linelen;
+ uint32_t associativity;
+ uint32_t nsets;
+ uint32_t cachesize;
+ /* info for set way operation on cache */
+ uint32_t index;
+ uint32_t index_shift;
+ uint32_t way;
+ uint32_t way_shift;
+};
-enum
-{
- ARM_PC = 15,
- ARM_CPSR = 16
-}
-;
-/* offsets into armv4_5 core register cache */
-enum
-{
- ARMV7A_CPSR = 31,
- ARMV7A_SPSR_FIQ = 32,
- ARMV7A_SPSR_IRQ = 33,
- ARMV7A_SPSR_SVC = 34,
- ARMV7A_SPSR_ABT = 35,
- ARMV7A_SPSR_UND = 36
+/* information about one architecture cache at any level */
+struct armv7a_arch_cache {
+ int ctype; /* cache type, CLIDR encoding */
+ struct armv7a_cachesize d_u_size; /* data cache */
+ struct armv7a_cachesize i_size; /* instruction cache */
};
-#define ARMV4_5_COMMON_MAGIC 0x0A450A45
-#define ARMV7_COMMON_MAGIC 0x0A450999
+/* common cache information */
+struct armv7a_cache_common {
+ int info; /* -1 invalid, else valid */
+ int loc; /* level of coherency */
+ uint32_t dminline; /* minimum d-cache linelen */
+ uint32_t iminline; /* minimum i-cache linelen */
+ struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */
+ int i_cache_enabled;
+ int d_u_cache_enabled;
+ int auto_cache_enabled; /* openocd automatic
+ * cache handling */
+ /* outer unified cache if some */
+ void *outer_cache;
+ int (*flush_all_data_cache)(struct target *target);
+};
-typedef struct armv7a_common_s
-{
- int common_magic;
- reg_cache_t *core_cache;
- enum armv7a_mode core_mode;
- enum armv7a_state core_state;
-
- /* arm adp debug port */
- swjdp_common_t swjdp_info;
- armv4_5_mmu_common_t armv4_5_mmu;
- armv4_5_common_t armv4_5_common;
- void *arch_info;
-
-// int (*full_context)(struct target_s *target);
-// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
-// int (*write_core_reg)(struct target_s *target, int num, enum armv7a_mode mode, u32 value);
- int (*read_cp15)(struct target_s *target,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm, uint32_t *value);
- int (*write_cp15)(struct target_s *target,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm, uint32_t value);
-
- int (*examine_debug_reason)(target_t *target);
- void (*pre_debug_entry)(target_t *target);
- void (*post_debug_entry)(target_t *target);
-
- void (*pre_restore_context)(target_t *target);
- void (*post_restore_context)(target_t *target);
-
-} armv7a_common_t;
-
-typedef struct armv7a_algorithm_s
-{
- int common_magic;
+struct armv7a_mmu_common {
+ /* following field mmu working way */
+ int32_t cached; /* 0: not initialized, 1: initialized */
+ uint32_t ttbcr; /* cache for ttbcr register */
+ uint32_t ttbr[2];
+ uint32_t ttbr_mask[2];
+ uint32_t ttbr_range[2];
+
+ int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer);
+ struct armv7a_cache_common armv7a_cache;
+ uint32_t mmu_enabled;
+};
- enum armv7a_mode core_mode;
- enum armv7a_state core_state;
-} armv7a_algorithm_t;
+struct armv7a_common {
+ struct arm arm;
+ int common_magic;
+ struct reg_cache *core_cache;
+
+ /* Core Debug Unit */
+ struct arm_dpm dpm;
+ uint32_t debug_base;
+ struct adiv5_ap *debug_ap;
+ struct adiv5_ap *memory_ap;
+ bool memory_ap_available;
+ /* mdir */
+ uint8_t multi_processor_system;
+ uint8_t cluster_id;
+ uint8_t cpu_id;
+ bool is_armv7r;
+ uint32_t rev;
+ uint32_t partnum;
+ uint32_t arch;
+ uint32_t variant;
+ uint32_t implementor;
+
+ /* cache specific to V7 Memory Management Unit compatible with v4_5*/
+ struct armv7a_mmu_common armv7a_mmu;
+
+ int (*examine_debug_reason)(struct target *target);
+ int (*post_debug_entry)(struct target *target);
+
+ void (*pre_restore_context)(struct target *target);
+};
-typedef struct armv7a_core_reg_s
+static inline struct armv7a_common *
+target_to_armv7a(struct target *target)
{
- int num;
- enum armv7a_mode mode;
- target_t *target;
- armv7a_common_t *armv7a_common;
-} armv7a_core_reg_t;
-
-int armv7a_arch_state(struct target_s *target);
-reg_cache_t *armv7a_build_reg_cache(target_t *target,
- armv7a_common_t *armv7a_common);
-int armv7a_register_commands(struct command_context_s *cmd_ctx);
-int armv7a_init_arch_info(target_t *target, armv7a_common_t *armv7a);
-
-/* map psr mode bits to linear number */
-static inline int armv7a_mode_to_number(enum armv7a_mode mode)
-{
- switch (mode)
- {
- case ARMV7A_MODE_USR: return 0; break;
- case ARMV7A_MODE_FIQ: return 1; break;
- case ARMV7A_MODE_IRQ: return 2; break;
- case ARMV7A_MODE_SVC: return 3; break;
- case ARMV7A_MODE_ABT: return 4; break;
- case ARMV7A_MODE_UND: return 5; break;
- case ARMV7A_MODE_SYS: return 6; break;
- case ARMV7A_MODE_MON: return 7; break;
- case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
- default:
- LOG_ERROR("invalid mode value encountered");
- return -1;
- }
+ return container_of(target->arch_info, struct armv7a_common, arm);
}
-/* map linear number to mode bits */
-static inline enum armv7a_mode armv7a_number_to_mode(int number)
+static inline bool is_armv7a(struct armv7a_common *armv7a)
{
- switch(number)
- {
- case 0: return ARMV7A_MODE_USR; break;
- case 1: return ARMV7A_MODE_FIQ; break;
- case 2: return ARMV7A_MODE_IRQ; break;
- case 3: return ARMV7A_MODE_SVC; break;
- case 4: return ARMV7A_MODE_ABT; break;
- case 5: return ARMV7A_MODE_UND; break;
- case 6: return ARMV7A_MODE_SYS; break;
- case 7: return ARMV7A_MODE_MON; break;
- default:
- LOG_ERROR("mode index out of bounds");
- return ARMV7A_MODE_ANY;
- }
-};
+ return armv7a->common_magic == ARMV7_COMMON_MAGIC;
+}
-#endif /* ARMV4_5_H */
+/* register offsets from armv7a.debug_base */
+
+/* See ARMv7a arch spec section C10.2 */
+#define CPUDBG_DIDR 0x000
+
+/* See ARMv7a arch spec section C10.3 */
+#define CPUDBG_WFAR 0x018
+/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
+#define CPUDBG_DSCR 0x088
+#define CPUDBG_DRCR 0x090
+#define CPUDBG_PRCR 0x310
+#define CPUDBG_PRSR 0x314
+
+/* See ARMv7a arch spec section C10.4 */
+#define CPUDBG_DTRRX 0x080
+#define CPUDBG_ITR 0x084
+#define CPUDBG_DTRTX 0x08c
+
+/* See ARMv7a arch spec section C10.5 */
+#define CPUDBG_BVR_BASE 0x100
+#define CPUDBG_BCR_BASE 0x140
+#define CPUDBG_WVR_BASE 0x180
+#define CPUDBG_WCR_BASE 0x1C0
+#define CPUDBG_VCR 0x01C
+
+/* See ARMv7a arch spec section C10.6 */
+#define CPUDBG_OSLAR 0x300
+#define CPUDBG_OSLSR 0x304
+#define CPUDBG_OSSRR 0x308
+#define CPUDBG_ECR 0x024
+
+/* See ARMv7a arch spec section C10.7 */
+#define CPUDBG_DSCCR 0x028
+#define CPUDBG_DSMCR 0x02C
+
+/* See ARMv7a arch spec section C10.8 */
+#define CPUDBG_AUTHSTATUS 0xFB8
+
+/* Masks for Vector Catch register */
+#define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
+#define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
+#define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
+#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
+#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
+
+int armv7a_arch_state(struct target *target);
+int armv7a_identify_cache(struct target *target);
+int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
+int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
+ uint32_t *val, int meminfo);
+int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
+
+int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+ struct armv7a_cache_common *armv7a_cache);
+
+extern const struct command_registration armv7a_command_handlers[];
+
+#endif /* OPENOCD_TARGET_ARMV7A_H */
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