+static inline struct armv7a_common *
+target_to_armv7a(struct target *target)
+{
+ return container_of(target->arch_info, struct armv7a_common, arm);
+}
+
+/* register offsets from armv7a.debug_base */
+
+/* See ARMv7a arch spec section C10.2 */
+#define CPUDBG_DIDR 0x000
+
+/* See ARMv7a arch spec section C10.3 */
+#define CPUDBG_WFAR 0x018
+/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
+#define CPUDBG_DSCR 0x088
+#define CPUDBG_DRCR 0x090
+#define CPUDBG_PRCR 0x310
+#define CPUDBG_PRSR 0x314
+
+/* See ARMv7a arch spec section C10.4 */
+#define CPUDBG_DTRRX 0x080
+#define CPUDBG_ITR 0x084
+#define CPUDBG_DTRTX 0x08c
+
+/* See ARMv7a arch spec section C10.5 */
+#define CPUDBG_BVR_BASE 0x100
+#define CPUDBG_BCR_BASE 0x140
+#define CPUDBG_WVR_BASE 0x180
+#define CPUDBG_WCR_BASE 0x1C0
+#define CPUDBG_VCR 0x01C
+
+/* See ARMv7a arch spec section C10.6 */
+#define CPUDBG_OSLAR 0x300
+#define CPUDBG_OSLSR 0x304
+#define CPUDBG_OSSRR 0x308
+#define CPUDBG_ECR 0x024
+
+/* See ARMv7a arch spec section C10.7 */
+#define CPUDBG_DSCCR 0x028
+
+/* See ARMv7a arch spec section C10.8 */
+#define CPUDBG_AUTHSTATUS 0xFB8
+
+int armv7a_arch_state(struct target *target);
+int armv7a_identify_cache(struct target *target);
+int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
+int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
+ uint32_t *val, int meminfo);
+int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
+
+int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+ struct armv7a_cache_common *armv7a_cache);
+
+extern const struct command_registration armv7a_command_handlers[];