Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / armv7m.c
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index ffc8ca875db0675a477fd11142d8ec207efaf41a..d508af7bf0c18d47b52a136c0f09427bc36c73d7 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
@@ -17,19 +19,6 @@
  *   Copyright (C) 2019 by Tomas Vanek                                     *
  *   vanekt@fbl.cz                                                         *
  *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
- *                                                                         *
  *   ARMv7-M Architecture, Application Level Reference Manual              *
  *              ARM DDI 0405C (September 2008)                             *
  *                                                                         *
@@ -64,7 +53,7 @@ const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
        ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
        ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
        ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
-       ARMV7M_xPSR,
+       ARMV7M_XPSR,
 };
 
 /* MSP is used in handler and some thread modes */
@@ -73,7 +62,7 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
        ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
        ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
        ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
-       ARMV7M_xPSR,
+       ARMV7M_XPSR,
 };
 
 /*
@@ -108,7 +97,7 @@ static const struct {
        { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
        { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
        { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
-       { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+       { ARMV7M_XPSR, "xpsr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 
        { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
@@ -127,27 +116,27 @@ static const struct {
        { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 
-       /* ARMv8-M specific registers */
-       { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
+       /* ARMv8-M security extension (TrustZone) specific registers */
+       { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
 
        { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
-       { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+       { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
 
        { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
-       { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+       { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
 
        /* FPU registers */
        { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
@@ -193,8 +182,11 @@ int armv7m_restore_context(struct target *target)
        for (i = cache->num_regs - 1; i >= 0; i--) {
                struct reg *r = &cache->reg_list[i];
 
-               if (r->exist && r->dirty)
-                       armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value);
+               if (r->exist && r->dirty) {
+                       int retval = armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value);
+                       if (retval != ERROR_OK)
+                               return retval;
+               }
        }
 
        return ERROR_OK;
@@ -251,12 +243,12 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
        return ERROR_OK;
 }
 
-static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
+uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
 {
        switch (arm_reg_id) {
        case ARMV7M_R0 ... ARMV7M_R14:
        case ARMV7M_PC:
-       case ARMV7M_xPSR:
+       case ARMV7M_XPSR:
        case ARMV7M_MSP:
        case ARMV7M_PSP:
                /* NOTE:  we "know" here that the register identifiers
@@ -289,7 +281,7 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
        }
 }
 
-static bool armv7m_map_reg_packing(unsigned int arm_reg_id,
+bool armv7m_map_reg_packing(unsigned int arm_reg_id,
                                        unsigned int *reg32_id, uint32_t *offset)
 {
 
@@ -492,7 +484,7 @@ int armv7m_run_algorithm(struct target *target,
        int num_mem_params, struct mem_param *mem_params,
        int num_reg_params, struct reg_param *reg_params,
        target_addr_t entry_point, target_addr_t exit_point,
-       int timeout_ms, void *arch_info)
+       unsigned int timeout_ms, void *arch_info)
 {
        int retval;
 
@@ -533,17 +525,23 @@ int armv7m_start_algorithm(struct target *target,
        }
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted (start target algo)");
                return ERROR_TARGET_NOT_HALTED;
        }
 
        /* Store all non-debug execution registers to armv7m_algorithm_info context */
        for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+               if (!reg->exist)
+                       continue;
+
+               if (!reg->valid)
+                       armv7m_get_core_reg(reg);
 
-               armv7m_algorithm_info->context[i] = buf_get_u32(
-                               armv7m->arm.core_cache->reg_list[i].value,
-                               0,
-                               32);
+               if (!reg->valid)
+                       LOG_TARGET_WARNING(target, "Storing invalid register %s", reg->name);
+
+               armv7m_algorithm_info->context[i] = buf_get_u32(reg->value, 0, 32);
        }
 
        for (int i = 0; i < num_mem_params; i++) {
@@ -590,7 +588,7 @@ int armv7m_start_algorithm(struct target *target,
                 * Because xPSR.T is populated on reset from the vector table,
                 * it might be 0 if the vector table has "bad" data in it.
                 */
-               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
                buf_set_u32(reg->value, 0, 32, 0x01000000);
                reg->valid = true;
                reg->dirty = true;
@@ -624,7 +622,7 @@ int armv7m_start_algorithm(struct target *target,
 int armv7m_wait_algorithm(struct target *target,
        int num_mem_params, struct mem_param *mem_params,
        int num_reg_params, struct reg_param *reg_params,
-       target_addr_t exit_point, int timeout_ms,
+       target_addr_t exit_point, unsigned int timeout_ms,
        void *arch_info)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
@@ -696,16 +694,19 @@ int armv7m_wait_algorithm(struct target *target,
        }
 
        for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+               if (!reg->exist)
+                       continue;
+
                uint32_t regvalue;
-               regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
+               regvalue = buf_get_u32(reg->value, 0, 32);
                if (regvalue != armv7m_algorithm_info->context[i]) {
                        LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
-                                       armv7m->arm.core_cache->reg_list[i].name,
-                               armv7m_algorithm_info->context[i]);
-                       buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
+                                         reg->name, armv7m_algorithm_info->context[i]);
+                       buf_set_u32(reg->value,
                                0, 32, armv7m_algorithm_info->context[i]);
-                       armv7m->arm.core_cache->reg_list[i].valid = true;
-                       armv7m->arm.core_cache->reg_list[i].dirty = true;
+                       reg->valid = true;
+                       reg->dirty = true;
                }
        }
 
@@ -737,8 +738,9 @@ int armv7m_arch_state(struct target *target)
        ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
        sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
-       LOG_USER("target halted due to %s, current mode: %s %s\n"
+       LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
                "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
+               target_name(target),
                debug_reason_name(target),
                arm_mode_name(arm->core_mode),
                armv7m_exception_string(armv7m->exception_number),
@@ -814,7 +816,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
                        LOG_ERROR("unable to allocate reg type list");
        }
 
-       arm->cpsr = reg_list + ARMV7M_xPSR;
+       arm->cpsr = reg_list + ARMV7M_XPSR;
        arm->pc = reg_list + ARMV7M_PC;
        arm->core_cache = cache;
 
@@ -865,6 +867,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
        /* Enable stimulus port #0 by default */
        armv7m->trace_config.itm_ter[0] = 1;
 
+       arm->core_state = ARM_STATE_THUMB;
        arm->core_type = ARM_CORE_TYPE_M_PROFILE;
        arm->arch_info = armv7m;
        arm->setup_semihosting = armv7m_setup_semihosting;
@@ -906,7 +909,7 @@ int armv7m_checksum_memory(struct target *target,
        buf_set_u32(reg_params[0].value, 0, 32, address);
        buf_set_u32(reg_params[1].value, 0, 32, count);
 
-       int timeout = 20000 * (1 + (count / (1024 * 1024)));
+       unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
 
        retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
                        crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6),
@@ -1013,7 +1016,7 @@ int armv7m_blank_check_memory(struct target *target,
        buf_set_u32(reg_params[1].value, 0, 32, erased_word);
 
        /* assume CPU clk at least 1 MHz */
-       int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
+       unsigned int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
 
        retval = target_run_algorithm(target,
                                0, NULL,
@@ -1095,7 +1098,11 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 
 const struct command_registration armv7m_command_handlers[] = {
        {
-               .chain = arm_command_handlers,
+               .name = "arm",
+               .mode = COMMAND_ANY,
+               .help = "ARM command group",
+               .usage = "",
+               .chain = arm_all_profiles_command_handlers,
        },
        COMMAND_REGISTRATION_DONE
 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)