#include "config.h"
#endif
-#include "replacements.h"
-
#include "armv7m.h"
-#include "register.h"
-#include "target.h"
-#include "log.h"
-#include "jtag.h"
-#include "arm_jtag.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
"primask", "basepri", "faultmask", "control"
};
-u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t armv7m_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
-u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
reg_t armv7m_gdb_dummy_fps_reg =
{
};
#ifdef ARMV7_GDB_HACKS
-u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
+uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
reg_t armv7m_gdb_dummy_cpsr_reg =
{
return retval;
}
-int armv7m_set_core_reg(reg_t *reg, u8 *buf)
+int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
{
armv7m_core_reg_t *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
- u32 value = buf_get_u32(buf, 0, 32);
+ uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
{
int armv7m_read_core_reg(struct target_s *target, int num)
{
- u32 reg_value;
+ uint32_t reg_value;
int retval;
armv7m_core_reg_t * armv7m_core_reg;
int armv7m_write_core_reg(struct target_s *target, int num)
{
int retval;
- u32 reg_value;
+ uint32_t reg_value;
armv7m_core_reg_t *armv7m_core_reg;
/* get pointers to arch-specific information */
armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
- LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
armv7m->core_cache->reg_list[num].valid = 1;
armv7m->core_cache->reg_list[num].dirty = 0;
/* ARMV7M is always in thumb mode, try to make GDB understand this
* if it does not support this arch */
- armv7m->core_cache->reg_list[15].value[0] |= 1;
+ *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
#else
(*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
#endif
}
/* run to exit point. return error if exit point was not reached. */
-static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int timeout_ms, u32 exit_point, armv7m_common_t *armv7m)
+static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
{
- u32 pc;
+ uint32_t pc;
int retval;
/* This code relies on the target specific resume() and poll()->debug_entry()
* sequence to write register values to the processor and the read them back */
- if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+ if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
{
return retval;
}
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
{
return retval;
}
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
if (pc != exit_point)
{
- LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
+ LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
return ERROR_OK;
}
-int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
enum armv7m_mode core_mode = armv7m->core_mode;
int retval = ERROR_OK;
int i;
- u32 context[ARMV7NUMCOREREGS];
+ uint32_t context[ARMV7NUMCOREREGS];
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
{
for (i = 0; i < num_mem_params; i++)
{
- if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
+ if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
return retval;
}
for (i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
- u32 regvalue;
+// uint32_t regvalue;
if (!reg)
{
exit(-1);
}
- regvalue = buf_get_u32(reg_params[i].value, 0, 32);
+// regvalue = buf_get_u32(reg_params[i].value, 0, 32);
armv7m_set_core_reg(reg, reg_params[i].value);
}
for (i = 0; i < num_mem_params; i++)
{
if (mem_params[i].direction != PARAM_OUT)
- if((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+ if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
{
return retval;
}
for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
{
- u32 regvalue;
+ uint32_t regvalue;
regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
if (regvalue != context[i])
{
- LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
armv7m->core_cache->reg_list[i].valid = 1;
armv7m->core_cache->reg_list[i].dirty = 1;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
+ LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
command_t *arm_adi_v5_dap_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
- register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num] (default 0)");
- register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "Displays debug base address from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", handle_dap_memaccess_command, COMMAND_EXEC, "set/get number of extra tck for mem-ap memory bus access [0-255]");
return ERROR_OK;
}
-int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
{
working_area_t *crc_algorithm;
armv7m_algorithm_t armv7m_info;
reg_param_t reg_params[2];
int retval;
- u16 cortex_m3_crc_code[] = {
+ uint16_t cortex_m3_crc_code[] = {
0x4602, /* mov r2, r0 */
0xF04F, 0x30FF, /* mov r0, #0xffffffff */
0x460B, /* mov r3, r1 */
0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
};
- u32 i;
+ uint32_t i;
if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
{
}
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
- if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i])) != ERROR_OK)
+ for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
+ if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
{
return retval;
}
buf_set_u32(reg_params[0].value, 0, 32, address);
buf_set_u32(reg_params[1].value, 0, 32, count);
- if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
+ if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
{
LOG_ERROR("error executing cortex_m3 crc algorithm");
return ERROR_OK;
}
-int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
+int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
{
working_area_t *erase_check_algorithm;
reg_param_t reg_params[3];
armv7m_algorithm_t armv7m_info;
int retval;
- u32 i;
+ uint32_t i;
- u16 erase_check_code[] =
+ uint16_t erase_check_code[] =
{
/* loop: */
0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
}
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
- target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
+ for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
+ target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARMV7M_MODE_ANY;
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
- if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
+ if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
{
destroy_reg_param(®_params[0]);
return ERROR_OK;
}
+/********************************************************************************************************************
+* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t apsel, apselsave, baseaddr;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
+
+/********************************************************************************************************************
+* Return the debug ap id in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t apsel, apselsave, apid;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8" PRIx32 "", apid);
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
- u32 apsel, apid;
+ uint32_t apsel, apid;
int retval;
apsel = 0;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
retval = swjdp_transaction_endcheck(swjdp);
- command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
+ command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8" PRIx32 "", (int)apsel, apid);
return retval;
}
+int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t memaccess_tck;
+
+ memaccess_tck = swjdp->memaccess_tck;
+ if (argc > 0)
+ {
+ memaccess_tck = strtoul(args[0], NULL, 0);
+ }
+
+ swjdp->memaccess_tck = memaccess_tck;
+ command_print(cmd_ctx, "memory bus access delay set to %i tck", (int)(swjdp->memaccess_tck));
+
+ return ERROR_OK;
+}
+
int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
- u32 apsel;
+ uint32_t apsel;
- apsel = 0;
+ apsel = swjdp->apsel;
if (argc > 0)
{
apsel = strtoul(args[0], NULL, 0);
Code Review / openocd.git / blobdiff