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target/armv7m: fix feature name of ARMv8M security extension regs
[openocd.git] / src / target / armv7m.c
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 790e70e63d506ab00773fde924e30f9db7f6d1a9..93df5877eb21de6ed0f7b7ff6625df0f7c55eb0a 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
@@ -53,7 +53,7 @@ const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
        ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
        ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
        ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
-       ARMV7M_xPSR,
+       ARMV7M_XPSR,
 };
 
 /* MSP is used in handler and some thread modes */
@@ -62,7 +62,7 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
        ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
        ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
        ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
-       ARMV7M_xPSR,
+       ARMV7M_XPSR,
 };
 
 /*
@@ -97,7 +97,7 @@ static const struct {
        { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
        { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
        { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
-       { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+       { ARMV7M_XPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 
        { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
@@ -116,27 +116,27 @@ static const struct {
        { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 
-       /* ARMv8-M specific registers */
-       { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
-       { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
+       /* ARMv8-M security extension (TrustZone) specific registers */
+       { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
 
        { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
-       { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+       { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
 
        { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
-       { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
-       { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+       { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+       { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
 
        /* FPU registers */
        { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
@@ -245,7 +245,7 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
        switch (arm_reg_id) {
        case ARMV7M_R0 ... ARMV7M_R14:
        case ARMV7M_PC:
-       case ARMV7M_xPSR:
+       case ARMV7M_XPSR:
        case ARMV7M_MSP:
        case ARMV7M_PSP:
                /* NOTE:  we "know" here that the register identifiers
@@ -528,11 +528,17 @@ int armv7m_start_algorithm(struct target *target,
 
        /* Store all non-debug execution registers to armv7m_algorithm_info context */
        for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+               if (!reg->exist)
+                       continue;
+
+               if (!reg->valid)
+                       armv7m_get_core_reg(reg);
+
+               if (!reg->valid)
+                       LOG_TARGET_WARNING(target, "Storing invalid register %s", reg->name);
 
-               armv7m_algorithm_info->context[i] = buf_get_u32(
-                               armv7m->arm.core_cache->reg_list[i].value,
-                               0,
-                               32);
+               armv7m_algorithm_info->context[i] = buf_get_u32(reg->value, 0, 32);
        }
 
        for (int i = 0; i < num_mem_params; i++) {
@@ -579,7 +585,7 @@ int armv7m_start_algorithm(struct target *target,
                 * Because xPSR.T is populated on reset from the vector table,
                 * it might be 0 if the vector table has "bad" data in it.
                 */
-               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
                buf_set_u32(reg->value, 0, 32, 0x01000000);
                reg->valid = true;
                reg->dirty = true;
@@ -685,16 +691,19 @@ int armv7m_wait_algorithm(struct target *target,
        }
 
        for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+               if (!reg->exist)
+                       continue;
+
                uint32_t regvalue;
-               regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
+               regvalue = buf_get_u32(reg->value, 0, 32);
                if (regvalue != armv7m_algorithm_info->context[i]) {
                        LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
-                                       armv7m->arm.core_cache->reg_list[i].name,
-                               armv7m_algorithm_info->context[i]);
-                       buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
+                                         reg->name, armv7m_algorithm_info->context[i]);
+                       buf_set_u32(reg->value,
                                0, 32, armv7m_algorithm_info->context[i]);
-                       armv7m->arm.core_cache->reg_list[i].valid = true;
-                       armv7m->arm.core_cache->reg_list[i].dirty = true;
+                       reg->valid = true;
+                       reg->dirty = true;
                }
        }
 
@@ -726,8 +735,9 @@ int armv7m_arch_state(struct target *target)
        ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
        sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
-       LOG_USER("target halted due to %s, current mode: %s %s\n"
+       LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
                "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
+               target_name(target),
                debug_reason_name(target),
                arm_mode_name(arm->core_mode),
                armv7m_exception_string(armv7m->exception_number),
@@ -803,7 +813,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
                        LOG_ERROR("unable to allocate reg type list");
        }
 
-       arm->cpsr = reg_list + ARMV7M_xPSR;
+       arm->cpsr = reg_list + ARMV7M_XPSR;
        arm->pc = reg_list + ARMV7M_PC;
        arm->core_cache = cache;
 
@@ -1085,7 +1095,11 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 
 const struct command_registration armv7m_command_handlers[] = {
        {
-               .chain = arm_command_handlers,
+               .name = "arm",
+               .mode = COMMAND_ANY,
+               .help = "ARM command group",
+               .usage = "",
+               .chain = arm_all_profiles_command_handlers,
        },
        COMMAND_REGISTRATION_DONE
 };
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