- preserve cortex_m3 C_MASKINTS during resume/step

[openocd.git] / src / target / armv7m.c

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 3897c231be78f7a2dfa19c458a9cceebb275a0d3..d4c6d3576f345c41fea80068b812326f2211fec1 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -303,14 +303,14 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim
        u32 pc;
        int retval;
        /* This code relies on the target specific  resume() and  poll()->debug_entry()
-       sequence to write register values to the processor and the read them back */
+        * sequence to write register values to the processor and the read them back */
        if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
        {
                return retval;
        }
 
        retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
-       // If the target fails to halt due to the breakpoint, force a halt
+       /* If the target fails to halt due to the breakpoint, force a halt */
        if (retval != ERROR_OK || target->state != TARGET_HALTED)
        {
                if ((retval=target_halt(target))!=ERROR_OK)
@@ -322,7 +322,6 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim
                return ERROR_TARGET_TIMEOUT;
        }
 
-
        armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
        if (pc != exit_point)
        {
@@ -340,7 +339,6 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
        armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
        enum armv7m_mode core_mode = armv7m->core_mode;
        int retval = ERROR_OK;
-       u32 pc;
        int i;
        u32 context[ARMV7NUMCOREREGS];