#include <unistd.h>
#include "armv8_opcodes.h"
-#include "arm_opcodes.h"
#include "target.h"
#include "target_type.h"
return retval;
}
+static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val)
+{
+ LOG_ERROR("4K page Address translation need to add");
+ return ERROR_FAIL;
+}
+
/* method adapted to cortex A : reused arm v4 v5 method*/
int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
- uint32_t first_lvl_descriptor = 0x0;
- uint32_t second_lvl_descriptor = 0x0;
- int retval;
+ int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t ttb = 0; /* default ttb0 */
- if (armv8->armv8_mmu.ttbr1_used == -1)
- armv8_read_ttbcr(target);
- if ((armv8->armv8_mmu.ttbr1_used) &&
- (va > (0xffffffff & armv8->armv8_mmu.ttbr0_mask))) {
- /* select ttb 1 */
- ttb = 1;
- }
+
retval = dpm->prepare(dpm);
+ retval += armv8_read_ttbcr(target);
if (retval != ERROR_OK)
goto done;
-
- /* MRC p15,0,<Rt>,c2,c0,ttb */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
- 4, 1, (uint8_t *)&first_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
- &first_lvl_descriptor);
- /* reuse armv4_5 piece of code, specific armv8 changes may come later */
- LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
-
- if ((first_lvl_descriptor & 0x3) == 0) {
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
- }
-
-
- if ((first_lvl_descriptor & 0x3) == 2) {
- /* section descriptor */
- *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
- return ERROR_OK;
- }
-
- if ((first_lvl_descriptor & 0x3) == 1) {
- /* coarse page table */
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- } else if ((first_lvl_descriptor & 0x3) == 3) {
- /* fine page table */
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- }
-
- second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
- &second_lvl_descriptor);
-
- LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
-
- if ((second_lvl_descriptor & 0x3) == 0) {
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
- }
-
- if ((second_lvl_descriptor & 0x3) == 1) {
- /* large page descriptor */
- *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 2) {
- /* small page descriptor */
- *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 3) {
- *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
- return ERROR_OK;
- }
-
- /* should not happen */
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
+ if (armv8->page_size == 0)
+ return armv8_4K_translate(target, va, val);
done:
- return retval;
+ dpm->finish(dpm);
+ return ERROR_FAIL;
}
/* V8 method VA TO PA */
/* DCCISW */
/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
+ ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
value);
if (retval != ERROR_OK)
goto done;
int armv8_identify_cache(struct target *target)
{
- /* read cache descriptor */
+ /* read cache descriptor */
int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
uint32_t cache_selected, clidr;
uint32_t cache_i_reg, cache_d_reg;
struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
- if (!armv8->is_armv7r)
- armv8_read_ttbcr(target);
+ armv8_read_ttbcr(target);
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
- /* retrieve CLIDR
- * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
+ /* retrieve CLIDR
+ * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
+ ARMV8_MRS(SYSTEM_CLIDR, 0),
&clidr);
if (retval != ERROR_OK)
goto done;
LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
if ((clidr / 2) > 1) {
/* FIXME not supported present in cortex A8 and later */
- /* in cortex A7, A15 */
+ /* in cortex A7, A15 */
LOG_ERROR("cache l2 present :not supported");
}
- /* retrieve selected cache
- * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
+ /* retrieve selected cache*/
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
&cache_selected);
if (retval != ERROR_OK)
goto done;
- retval = armv8->arm.mrc(target, 15,
- 2, 0, /* op1, op2 */
- 0, 0, /* CRn, CRm */
- &cache_selected);
- if (retval != ERROR_OK)
- goto done;
+
/* select instruction cache
- * MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
- * [0] : 1 instruction cache selection , 0 data cache selection */
+ * [0] : 1 instruction cache selection , 0 data cache selection */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
1);
if (retval != ERROR_OK)
goto done;
/* read CCSIDR
* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
- * [2:0] line size 001 eight word per line
+ * [2:0] line size 001 eight word per line
* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CCSIDR, 0),
&cache_i_reg);
if (retval != ERROR_OK)
goto done;
- /* select data cache*/
+ /* select data cache*/
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
0);
if (retval != ERROR_OK)
goto done;
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CCSIDR, 0),
&cache_d_reg);
if (retval != ERROR_OK)
goto done;
- /* restore selected cache */
+ /* restore selected cache */
dpm->instr_write_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
cache_selected);
if (retval != ERROR_OK)
return ERROR_OK;
}
+int armv8_aarch64_state(struct target *target)
+{
+ struct arm *arm = target_to_arm(target);
+
+ if (arm->common_magic != ARM_COMMON_MAGIC) {
+ LOG_ERROR("BUG: called for a non-ARM target");
+ return ERROR_FAIL;
+ }
+
+ LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
+ armv8_state_strings[arm->core_state],
+ debug_reason_name(target),
+ armv8_mode_name(arm->core_mode),
+ buf_get_u32(arm->cpsr->value, 0, 32),
+ buf_get_u64(arm->pc->value, 0, 64),
+ arm->is_semihosting ? ", semihosting" : "");
+
+ return ERROR_OK;
+}
+
int armv8_arch_state(struct target *target)
{
static const char * const state[] = {
return ERROR_COMMAND_SYNTAX_ERROR;
}
- arm_arch_state(target);
+ if (arm->core_state == ARM_STATE_AARCH64)
+ armv8_aarch64_state(target);
+ else
+ arm_arch_state(target);
- if (armv8->is_armv7r) {
- LOG_USER("D-Cache: %s, I-Cache: %s",
- state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
- state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
- } else {
- LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
- state[armv8->armv8_mmu.mmu_enabled],
- state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
- state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
- }
+ LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+ state[armv8->armv8_mmu.mmu_enabled],
+ state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
+ state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
if (arm->core_mode == ARM_MODE_ABT)
armv8_show_fault_registers(target);
{
struct reg *r;
- if (regnum > 33)
+ if (regnum > (ARMV8_LAST_REG - 1))
return NULL;
r = arm->core_cache->reg_list + regnum;
switch (reg_class) {
case REG_CLASS_GENERAL:
case REG_CLASS_ALL:
- *reg_list_size = 34;
+ *reg_list_size = ARMV8_LAST_REG;
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
- for (i = 0; i < *reg_list_size; i++)
+ for (i = 0; i < ARMV8_LAST_REG; i++)
(*reg_list)[i] = armv8_reg_current(arm, i);
return ERROR_OK;
- break;
default:
LOG_ERROR("not a valid register class type in query.");
Code Review / openocd.git / blobdiff