#include "target.h"
#include "target_type.h"
+#define __unused __attribute__((unused))
+
static const char * const armv8_state_strings[] = {
"AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
};
return ERROR_OK;
}
#endif
+
+/* retrieve core id cluster id */
+int armv8_read_mpidr(struct armv8_common *armv8)
+{
+ int retval = ERROR_FAIL;
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ uint32_t mpidr;
+
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
+ if (retval != ERROR_OK)
+ goto done;
+ if (mpidr & 1<<31) {
+ armv8->multi_processor_system = (mpidr >> 30) & 1;
+ armv8->cluster_id = (mpidr >> 8) & 0xf;
+ armv8->cpu_id = mpidr & 0x3;
+ LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
+ armv8->cluster_id,
+ armv8->cpu_id,
+ armv8->multi_processor_system == 0 ? "multi core" : "mono core");
+
+ } else
+ LOG_ERROR("mpdir not in multiprocessor format");
+
+done:
+ dpm->finish(dpm);
+ return retval;
+}
+
/**
* Configures host-side ARM records to reflect the specified CPSR.
* Later, code can use arm_reg_current() to map register numbers
}
}
arm->core_state = state;
- if (arm->core_state == ARM_STATE_AARCH64) {
- switch (mode) {
- case SYSTEM_AAR64_MODE_EL0t:
- arm->core_mode = ARMV8_64_EL0T;
- break;
- case SYSTEM_AAR64_MODE_EL1t:
- arm->core_mode = ARMV8_64_EL0T;
- break;
- case SYSTEM_AAR64_MODE_EL1h:
- arm->core_mode = ARMV8_64_EL1H;
- break;
- case SYSTEM_AAR64_MODE_EL2t:
- arm->core_mode = ARMV8_64_EL2T;
- break;
- case SYSTEM_AAR64_MODE_EL2h:
- arm->core_mode = ARMV8_64_EL2H;
- break;
- case SYSTEM_AAR64_MODE_EL3t:
- arm->core_mode = ARMV8_64_EL3T;
- break;
- case SYSTEM_AAR64_MODE_EL3h:
- arm->core_mode = ARMV8_64_EL3H;
- break;
- default:
- LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
- break;
- }
- } else {
+ if (arm->core_state == ARM_STATE_AARCH64)
+ arm->core_mode = (mode << 4) | 0xf;
+ else
arm->core_mode = mode;
- }
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv8_mode_name(arm->core_mode),
return ret;
}
-static int armv8_read_ttbcr32(struct target *target)
+static __unused int armv8_read_ttbcr32(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
return retval;
}
-static int armv8_read_ttbcr(struct target *target)
+static __unused int armv8_read_ttbcr(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
if (retval != ERROR_OK)
goto done;
-#if 0
- LOG_INFO("ttb1 %s ,ttb0_mask %llx",
- armv8->armv8_mmu.ttbr1_used ? "used" : "not used",
- armv8->armv8_mmu.ttbr0_mask);
-#endif
- if (armv8->armv8_mmu.ttbr1_used == 1) {
- LOG_INFO("TTBR0 access above %" PRIx64,
- (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
- armv8->armv8_mmu.os_border = armv8->armv8_mmu.ttbr0_mask;
- } else {
- /* fix me , default is hard coded LINUX border */
- armv8->armv8_mmu.os_border = 0xc0000000;
- }
+ if (armv8->armv8_mmu.ttbr1_used == 1)
+ LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
+
done:
dpm->finish(dpm);
return retval;
}
-static int armv8_4K_translate(struct target *target, target_addr_t va, target_addr_t *val)
-{
- LOG_ERROR("4K page Address translation need to add");
- return ERROR_FAIL;
-}
-
-
/* method adapted to cortex A : reused arm v4 v5 method*/
int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
{
- int retval = ERROR_FAIL;
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
-
- retval = dpm->prepare(dpm);
- retval += armv8_read_ttbcr(target);
- if (retval != ERROR_OK)
- goto done;
- if (armv8->page_size == 0)
- return armv8_4K_translate(target, va, val);
-
-done:
- dpm->finish(dpm);
- return ERROR_FAIL;
+ return ERROR_OK;
}
/* V8 method VA TO PA */
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
target_addr_t *val, int meminfo)
{
- return ERROR_OK;
-}
-
-static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
- struct armv8_cache_common *armv8_cache)
-{
- if (armv8_cache->ctype == -1) {
- command_print(cmd_ctx, "cache not yet identified");
- return ERROR_OK;
- }
-
- command_print(cmd_ctx,
- "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
- armv8_cache->d_u_size.linelen,
- armv8_cache->d_u_size.associativity,
- armv8_cache->d_u_size.nsets,
- armv8_cache->d_u_size.cachesize);
+ struct armv8_common *armv8 = target_to_armv8(target);
+ struct arm *arm = target_to_arm(target);
+ struct arm_dpm *dpm = &armv8->dpm;
+ uint32_t retval;
+ uint32_t instr = 0;
+ uint64_t par;
- command_print(cmd_ctx,
- "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
- armv8_cache->i_size.linelen,
- armv8_cache->i_size.associativity,
- armv8_cache->i_size.nsets,
- armv8_cache->i_size.cachesize);
+ static const char * const shared_name[] = {
+ "Non-", "UNDEFINED ", "Outer ", "Inner "
+ };
- return ERROR_OK;
-}
+ static const char * const secure_name[] = {
+ "Secure", "Not Secure"
+ };
-static int _armv8_flush_all_data(struct target *target)
-{
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
- struct armv8_cachesize *d_u_size =
- &(armv8->armv8_mmu.armv8_cache.d_u_size);
- int32_t c_way, c_index = d_u_size->index;
- int retval;
- /* check that cache data is on at target halt */
- if (!armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
- LOG_INFO("flushed not performed :cache not on at target halt");
- return ERROR_OK;
- }
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
- goto done;
- do {
- c_way = d_u_size->way;
- do {
- uint32_t value = (c_index << d_u_size->index_shift)
- | (c_way << d_u_size->way_shift);
- /* DCCISW */
- /* LOG_INFO ("%d %d %x",c_way,c_index,value); */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
- value);
- if (retval != ERROR_OK)
- goto done;
- c_way -= 1;
- } while (c_way >= 0);
- c_index -= 1;
- } while (c_index >= 0);
- return retval;
-done:
- LOG_ERROR("flushed failed");
- dpm->finish(dpm);
- return retval;
-}
-
-static int armv8_flush_all_data(struct target *target)
-{
- int retval = ERROR_FAIL;
- /* check that armv8_cache is correctly identify */
- struct armv8_common *armv8 = target_to_armv8(target);
- if (armv8->armv8_mmu.armv8_cache.ctype == -1) {
- LOG_ERROR("trying to flush un-identified cache");
return retval;
- }
-
- if (target->smp) {
- /* look if all the other target have been flushed in order to flush level
- * 2 */
- struct target_list *head;
- struct target *curr;
- head = target->head;
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- if (curr->state == TARGET_HALTED) {
- LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
- retval = _armv8_flush_all_data(curr);
- }
- head = head->next;
- }
- } else
- retval = _armv8_flush_all_data(target);
- return retval;
-}
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
- struct armv8_cache_common *armv8_cache)
-{
- if (armv8_cache->ctype == -1) {
- command_print(cmd_ctx, "cache not yet identified");
- return ERROR_OK;
- }
-
- if (armv8_cache->display_cache_info)
- armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
- return ERROR_OK;
-}
-
-/* retrieve core id cluster id */
-static int armv8_read_mpidr(struct target *target)
-{
- int retval = ERROR_FAIL;
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t mpidr;
-
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- goto done;
- /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
+ switch (armv8_curel_from_core_mode(arm)) {
+ case SYSTEM_CUREL_EL0:
+ instr = ARMV8_SYS(SYSTEM_ATS12E0R, 0);
+ /* can only execute instruction at EL2 */
+ dpmv8_modeswitch(dpm, ARMV8_64_EL2T);
+ break;
+ case SYSTEM_CUREL_EL1:
+ instr = ARMV8_SYS(SYSTEM_ATS12E1R, 0);
+ /* can only execute instruction at EL2 */
+ dpmv8_modeswitch(dpm, ARMV8_64_EL2T);
+ break;
+ case SYSTEM_CUREL_EL2:
+ instr = ARMV8_SYS(SYSTEM_ATS1E2R, 0);
+ break;
+ case SYSTEM_CUREL_EL3:
+ instr = ARMV8_SYS(SYSTEM_ATS1E3R, 0);
+ break;
- retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
- if (retval != ERROR_OK)
- goto done;
- if (mpidr & 1<<31) {
- armv8->multi_processor_system = (mpidr >> 30) & 1;
- armv8->cluster_id = (mpidr >> 8) & 0xf;
- armv8->cpu_id = mpidr & 0x3;
- LOG_INFO("%s cluster %x core %x %s", target_name(target),
- armv8->cluster_id,
- armv8->cpu_id,
- armv8->multi_processor_system == 0 ? "multi core" : "mono core");
+ default:
+ break;
+ };
- } else
- LOG_ERROR("mpdir not in multiprocessor format");
+ /* write VA to R0 and execute translation instruction */
+ retval = dpm->instr_write_data_r0_64(dpm, instr, (uint64_t)va);
+ /* read result from PAR_EL1 */
+ if (retval == ERROR_OK)
+ retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_PAR_EL1, 0), &par);
-done:
dpm->finish(dpm);
- return retval;
-
-}
-
-int armv8_identify_cache(struct target *target)
-{
- /* read cache descriptor */
- int retval = ERROR_FAIL;
- struct armv8_common *armv8 = target_to_armv8(target);
- struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t cache_selected, clidr;
- uint32_t cache_i_reg, cache_d_reg;
- struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
- int is_aarch64 = armv8->arm.core_state == ARM_STATE_AARCH64;
+ /* switch back to saved PE mode */
+ dpmv8_modeswitch(dpm, ARM_MODE_ANY);
- retval = is_aarch64 ? armv8_read_ttbcr(target) : armv8_read_ttbcr32(target);
if (retval != ERROR_OK)
return retval;
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- goto done;
-
- /* retrieve CLIDR */
- retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
- if (retval != ERROR_OK)
- goto done;
-
- clidr = (clidr & 0x7000000) >> 23;
- LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
- if ((clidr / 2) > 1) {
- /* FIXME not supported present in cortex A8 and later */
- /* in cortex A7, A15 */
- LOG_ERROR("cache l2 present :not supported");
- }
- /* retrieve selected cache*/
- retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CSSELR), &cache_selected);
- if (retval != ERROR_OK)
- goto done;
+ if (par & 1) {
+ LOG_ERROR("Address translation failed at stage %i, FST=%x, PTW=%i",
+ ((int)(par >> 9) & 1)+1, (int)(par >> 1) & 0x3f, (int)(par >> 8) & 1);
- /* select instruction cache
- * [0] : 1 instruction cache selection , 0 data cache selection */
- retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 1);
- if (retval != ERROR_OK)
- goto done;
-
- /* read CCSIDR
- * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
- * [2:0] line size 001 eight word per line
- * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
- retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_i_reg);
- if (retval != ERROR_OK)
- goto done;
-
- /* select data cache*/
- retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 0);
- if (retval != ERROR_OK)
- goto done;
-
- retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_d_reg);
- if (retval != ERROR_OK)
- goto done;
+ *val = 0;
+ retval = ERROR_FAIL;
+ } else {
+ *val = (par & 0xFFFFFFFFF000UL) | (va & 0xFFF);
+ if (meminfo) {
+ int SH = (par >> 7) & 3;
+ int NS = (par >> 9) & 1;
+ int ATTR = (par >> 56) & 0xFF;
- /* restore selected cache */
- dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), cache_selected);
- if (retval != ERROR_OK)
- goto done;
- dpm->finish(dpm);
+ char *memtype = (ATTR & 0xF0) == 0 ? "Device Memory" : "Normal Memory";
- /* put fake type */
- cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
- cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
- cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
- cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
- /* compute info for set way operation on cache */
- cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
- cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
- cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
- cache->d_u_size.way_shift = cache->d_u_size.way + 1;
- {
- int i = 0;
- while (((cache->d_u_size.way_shift >> i) & 1) != 1)
- i++;
- cache->d_u_size.way_shift = 32-i;
- }
-#if 0
- LOG_INFO("data cache index %d << %d, way %d << %d",
- cache->d_u_size.index, cache->d_u_size.index_shift,
- cache->d_u_size.way,
- cache->d_u_size.way_shift);
-
- LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
- cache->d_u_size.linelen,
- cache->d_u_size.cachesize,
- cache->d_u_size.associativity);
-#endif
- cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
- cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
- cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
- cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
- /* compute info for set way operation on cache */
- cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
- cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
- cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
- cache->i_size.way_shift = cache->i_size.way + 1;
- {
- int i = 0;
- while (((cache->i_size.way_shift >> i) & 1) != 1)
- i++;
- cache->i_size.way_shift = 32-i;
- }
-#if 0
- LOG_INFO("instruction cache index %d << %d, way %d << %d",
- cache->i_size.index, cache->i_size.index_shift,
- cache->i_size.way, cache->i_size.way_shift);
-
- LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
- cache->i_size.linelen,
- cache->i_size.cachesize,
- cache->i_size.associativity);
-#endif
- /* if no l2 cache initialize l1 data cache flush function function */
- if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
- armv8->armv8_mmu.armv8_cache.display_cache_info =
- armv8_handle_inner_cache_info_command;
- armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
- armv8_flush_all_data;
+ LOG_USER("%sshareable, %s",
+ shared_name[SH], secure_name[NS]);
+ LOG_USER("%s", memtype);
+ }
}
- armv8->armv8_mmu.armv8_cache.ctype = 0;
-done:
- dpm->finish(dpm);
- armv8_read_mpidr(target);
return retval;
+}
+
+int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+ struct armv8_cache_common *armv8_cache)
+{
+ if (armv8_cache->info == -1) {
+ command_print(cmd_ctx, "cache not yet identified");
+ return ERROR_OK;
+ }
+ if (armv8_cache->display_cache_info)
+ armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
+ return ERROR_OK;
}
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
#endif
armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
- armv8->armv8_mmu.armv8_cache.ctype = -1;
+ armv8->armv8_mmu.armv8_cache.info = -1;
armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
return ERROR_OK;
Code Review / openocd.git / blobdiff