struct armv8_cachesize {
uint32_t level_num;
- /* cache dimensionning */
+ /* cache dimensioning */
uint32_t linelen;
uint32_t associativity;
uint32_t nsets;
/* l2 external unified cache if some */
void *l2_cache;
int (*flush_all_data_cache)(struct target *target);
- int (*display_cache_info)(struct command_context *cmd_ctx,
+ int (*display_cache_info)(struct command_invocation *cmd,
struct armv8_cache_common *armv8_cache);
};
/* Core Debug Unit */
struct arm_dpm dpm;
- uint32_t debug_base;
+ target_addr_t debug_base;
struct adiv5_ap *debug_ap;
const uint32_t *opcodes;
#define CPUV8_DBG_EDESR 0x20
#define CPUV8_DBG_EDECR 0x24
-#define CPUV8_DBG_WFAR0 0x30
-#define CPUV8_DBG_WFAR1 0x34
+#define CPUV8_DBG_EDWAR0 0x30
+#define CPUV8_DBG_EDWAR1 0x34
#define CPUV8_DBG_DSCR 0x088
#define CPUV8_DBG_DRCR 0x090
+#define CPUV8_DBG_ECCR 0x098
#define CPUV8_DBG_PRCR 0x310
#define CPUV8_DBG_PRSR 0x314
target_addr_t *val, int meminfo);
int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
struct armv8_cache_common *armv8_cache);
void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
}
}
+const char *armv8_mode_name(unsigned psr_mode);
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);