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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / armv8_cache.c
diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index f496c3cf0519cb14c90d63cb2eba74d5855c94e0..66d4e00801cde44f7976236c5698aa4501acfccb 100644 (file)
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /***************************************************************************
  *   Copyright (C) 2016 by Matthias Welwarsky                              *
  *   matthias.welwarsky@sysgo.com                                          *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -23,6 +12,7 @@
 #include "armv8_cache.h"
 #include "armv8_dpm.h"
 #include "armv8_opcodes.h"
+#include "smp.h"
 
 /* CLIDR cache types */
 #define CACHE_LEVEL_HAS_UNIFIED_CACHE  0x4
@@ -49,8 +39,9 @@ static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
        return ERROR_TARGET_INVALID;
 }
 
-static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cachesize *size, int cl)
+static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct armv8_cachesize *size, int cl)
 {
+       struct arm_dpm *dpm = armv8->arm.dpm;
        int retval = ERROR_OK;
        int32_t c_way, c_index = size->index;
 
@@ -65,7 +56,7 @@ static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cac
                         * line by Set/Way.
                         */
                        retval = dpm->instr_write_data_r0(dpm,
-                                       ARMV8_SYS(SYSTEM_DCCISW, 0), value);
+                                       armv8_opcode(armv8, ARMV8_OPC_DCCISW), value);
                        if (retval != ERROR_OK)
                                goto done;
                        c_way -= 1;
@@ -97,7 +88,7 @@ static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
                if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
                        continue;
 
-               armv8_cache_d_inner_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
+               armv8_cache_d_inner_flush_level(armv8, &cache->arch[cl].d_u_size, cl);
        }
 
        retval = dpm->finish(dpm);
@@ -133,7 +124,7 @@ int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va,
                /* DC CIVAC */
                /* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
                retval = dpm->instr_write_data_r0_64(dpm,
-                               ARMV8_SYS(SYSTEM_DCCIVAC, 0), va_line);
+                               armv8_opcode(armv8, ARMV8_OPC_DCCIVAC), va_line);
                if (retval != ERROR_OK)
                        goto done;
                va_line += linelen;
@@ -171,7 +162,7 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
        while (va_line < va_end) {
                /* IC IVAU - Invalidate instruction cache by VA to PoU. */
                retval = dpm->instr_write_data_r0_64(dpm,
-                               ARMV8_SYS(SYSTEM_ICIVAU, 0), va_line);
+                               armv8_opcode(armv8, ARMV8_OPC_ICIVAU), va_line);
                if (retval != ERROR_OK)
                        goto done;
                va_line += linelen;
@@ -187,13 +178,13 @@ done:
        return retval;
 }
 
-static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
+static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
        struct armv8_cache_common *armv8_cache)
 {
        int cl;
 
        if (armv8_cache->info == -1) {
-               command_print(cmd_ctx, "cache not yet identified");
+               command_print(cmd, "cache not yet identified");
                return ERROR_OK;
        }
 
@@ -201,11 +192,11 @@ static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx
                struct armv8_arch_cache *arch = &(armv8_cache->arch[cl]);
 
                if (arch->ctype & 1) {
-                       command_print(cmd_ctx,
-                               "L%d I-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
+                       command_print(cmd,
+                               "L%d I-Cache: linelen %" PRIu32
+                               ", associativity %" PRIu32
+                               ", nsets %" PRIu32
+                               ", cachesize %" PRIu32 " KBytes",
                                cl+1,
                                arch->i_size.linelen,
                                arch->i_size.associativity,
@@ -214,11 +205,11 @@ static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx
                }
 
                if (arch->ctype >= 2) {
-                       command_print(cmd_ctx,
-                               "L%d D-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
+                       command_print(cmd,
+                               "L%d D-Cache: linelen %" PRIu32
+                               ", associativity %" PRIu32
+                               ", nsets %" PRIu32
+                               ", cachesize %" PRIu32 " KBytes",
                                cl+1,
                                arch->d_u_size.linelen,
                                arch->d_u_size.associativity,
@@ -249,15 +240,12 @@ static int  armv8_flush_all_data(struct target *target)
                /*  look if all the other target have been flushed in order to flush level
                 *  2 */
                struct target_list *head;
-               struct target *curr;
-               head = target->head;
-               while (head != (struct target_list *)NULL) {
-                       curr = head->target;
+               foreach_smp_target(head, target->smp_targets) {
+                       struct target *curr = head->target;
                        if (curr->state == TARGET_HALTED) {
-                               LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
+                               LOG_TARGET_INFO(curr, "Wait flushing data l1.");
                                retval = _armv8_flush_all_data(curr);
                        }
-                       head = head->next;
                }
        } else
                retval = _armv8_flush_all_data(target);
@@ -266,17 +254,18 @@ static int  armv8_flush_all_data(struct target *target)
 
 static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
 {
+       struct armv8_common *armv8 = dpm->arm->arch_info;
        int retval = ERROR_OK;
 
        /*  select cache level */
        retval = dpm->instr_write_data_r0(dpm,
-                       ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
+                       armv8_opcode(armv8, WRITE_REG_CSSELR),
                        (cl << 1) | (ct == 1 ? 1 : 0));
        if (retval != ERROR_OK)
                goto done;
 
        retval = dpm->instr_read_data_r0(dpm,
-                       ARMV8_MRS(SYSTEM_CCSIDR, 0),
+                       armv8_opcode(armv8, READ_REG_CCSIDR),
                        cache_reg);
  done:
        return retval;
@@ -297,8 +286,9 @@ static struct armv8_cachesize decode_cache_reg(uint32_t cache_reg)
        size.index = (cache_reg >> 13) & 0x7fff;
        size.way = ((cache_reg >> 3) & 0x3ff);
 
-       while (((size.way << i) & 0x80000000) == 0)
-               i++;
+       if (size.way != 0)
+               while (((size.way << i) & 0x80000000) == 0)
+                       i++;
        size.way_shift = i;
 
        return size;
@@ -308,6 +298,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 {
        /*  read cache descriptor */
        int retval = ERROR_FAIL;
+       struct arm *arm = &armv8->arm;
        struct arm_dpm *dpm = armv8->arm.dpm;
        uint32_t csselr, clidr, ctr;
        uint32_t cache_reg;
@@ -318,18 +309,27 @@ int armv8_identify_cache(struct armv8_common *armv8)
        if (retval != ERROR_OK)
                goto done;
 
+       /* check if we're in an unprivileged mode */
+       if (armv8_curel_from_core_mode(arm->core_mode) < SYSTEM_CUREL_EL1) {
+               retval = armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
+
        /* retrieve CTR */
-       retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CTR, 0), &ctr);
+       retval = dpm->instr_read_data_r0(dpm,
+                       armv8_opcode(armv8, READ_REG_CTR), &ctr);
        if (retval != ERROR_OK)
                goto done;
 
        cache->iminline = 4UL << (ctr & 0xf);
        cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
                 ctr, cache->iminline, cache->dminline);
 
        /*  retrieve CLIDR */
-       retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CLIDR, 0), &clidr);
+       retval = dpm->instr_read_data_r0(dpm,
+                       armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
        if (retval != ERROR_OK)
                goto done;
 
@@ -338,7 +338,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
 
        /*  retrieve selected cache for later restore
         *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
-       retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CSSELR, 0), &csselr);
+       retval = dpm->instr_read_data_r0(dpm,
+                       armv8_opcode(armv8, READ_REG_CSSELR), &csselr);
        if (retval != ERROR_OK)
                goto done;
 
@@ -360,13 +361,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
                                goto done;
                        cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+                       LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].d_u_size.index,
                                        cache->arch[cl].d_u_size.index_shift,
                                        cache->arch[cl].d_u_size.way,
                                        cache->arch[cl].d_u_size.way_shift);
 
-                       LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].d_u_size.linelen,
                                        cache->arch[cl].d_u_size.cachesize,
                                        cache->arch[cl].d_u_size.associativity);
@@ -380,13 +381,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
                                goto done;
                        cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+                       LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].i_size.index,
                                        cache->arch[cl].i_size.index_shift,
                                        cache->arch[cl].i_size.way,
                                        cache->arch[cl].i_size.way_shift);
 
-                       LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].i_size.linelen,
                                        cache->arch[cl].i_size.cachesize,
                                        cache->arch[cl].i_size.associativity);
@@ -396,14 +397,15 @@ int armv8_identify_cache(struct armv8_common *armv8)
        }
 
        /*  restore selected cache  */
-       dpm->instr_write_data_r0(dpm, ARMV8_MSR_GP(SYSTEM_CSSELR, 0), csselr);
+       dpm->instr_write_data_r0(dpm,
+                       armv8_opcode(armv8, WRITE_REG_CSSELR), csselr);
        if (retval != ERROR_OK)
                goto done;
 
        armv8->armv8_mmu.armv8_cache.info = 1;
 
        /*  if no l2 cache initialize l1 data cache flush function function */
-       if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
+       if (!armv8->armv8_mmu.armv8_cache.flush_all_data_cache) {
                armv8->armv8_mmu.armv8_cache.display_cache_info =
                        armv8_handle_inner_cache_info_command;
                armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
@@ -411,6 +413,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
        }
 
 done:
+       armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
        dpm->finish(dpm);
        return retval;
 
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