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aarch64: don't try resuming if target is not halted
[openocd.git] / src / target / armv8_dpm.c
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 8caa8b60cbc2a12ef2c252c11c11bf7c0dd90a65..b4c14c2c031fea5c3d97545ffd6961a9b08d64d5 100644 (file)
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -79,11 +79,11 @@ static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
 static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data)
 {
        int ret;
-       LOG_DEBUG("write DCC Low word 0x%08" PRIx32, (unsigned)data);
-       LOG_DEBUG("write DCC High word 0x%08" PRIx32, (unsigned)(data >> 32));
+       LOG_DEBUG("write DCC 0x%016" PRIx64, data);
        ret = mem_ap_write_u32(armv8->debug_ap,
                               armv8->debug_base + CPUV8_DBG_DTRRX, data);
-       ret += mem_ap_write_u32(armv8->debug_ap,
+       if (ret == ERROR_OK)
+               ret = mem_ap_write_u32(armv8->debug_ap,
                                armv8->debug_base + CPUV8_DBG_DTRTX, data >> 32);
        return ret;
 }
@@ -143,7 +143,7 @@ static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
                if (retval != ERROR_OK)
                        return retval;
                if (timeval_ms() > then + 1000) {
-                       LOG_ERROR("Timeout waiting for read dcc");
+                       LOG_ERROR("Timeout waiting for DTR_TX_FULL, dscr = 0x%08" PRIx32, dscr);
                        return ERROR_FAIL;
                }
        }
@@ -175,7 +175,7 @@ static int dpmv8_dpm_prepare(struct arm_dpm *dpm)
        uint32_t dscr;
        int retval;
 
-       /* set up invariant:  INSTR_COMP is set after ever DPM operation */
+       /* set up invariant:  ITE is set after ever DPM operation */
        long long then = timeval_ms();
        for (;; ) {
                retval = mem_ap_read_atomic_u32(armv8->debug_ap,
@@ -202,12 +202,6 @@ static int dpmv8_dpm_prepare(struct arm_dpm *dpm)
                        armv8->debug_base + CPUV8_DBG_DTRRX, &dscr);
                if (retval != ERROR_OK)
                        return retval;
-
-               /* Clear sticky error */
-               retval = mem_ap_write_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
-               if (retval != ERROR_OK)
-                       return retval;
        }
 
        return retval;
@@ -223,7 +217,7 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm,
        uint32_t opcode, uint32_t *p_dscr)
 {
        struct armv8_common *armv8 = dpm->arm->arch_info;
-       uint32_t dscr = DSCR_ITE;
+       uint32_t dscr = dpm->dscr;
        int retval;
 
        LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
@@ -276,9 +270,6 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm,
 
        if (dscr & DSCR_ERR) {
                LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
-               /* clear the sticky error condition */
-               mem_ap_write_atomic_u32(armv8->debug_ap,
-                               armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
                armv8_dpm_handle_exception(dpm);
                retval = ERROR_FAIL;
        }
@@ -343,19 +334,18 @@ static int dpmv8_instr_write_data_r0_64(struct arm_dpm *dpm,
        uint32_t opcode, uint64_t data)
 {
        struct armv8_common *armv8 = dpm->arm->arch_info;
-       uint32_t dscr = DSCR_ITE;
        int retval;
 
+       /* transfer data from DCC to R0 */
        retval = dpmv8_write_dcc_64(armv8, data);
-       if (retval != ERROR_OK)
-               return retval;
-
-       retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
-       if (retval != ERROR_OK)
-               return retval;
+       if (retval == ERROR_OK)
+               retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
 
        /* then the opcode, taking data from R0 */
-       return dpmv8_exec_opcode(dpm, opcode, &dscr);
+       if (retval == ERROR_OK)
+               retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
+
+       return retval;
 }
 
 static int dpmv8_instr_cpsr_sync(struct arm_dpm *dpm)
@@ -374,70 +364,66 @@ static int dpmv8_instr_read_data_dcc(struct arm_dpm *dpm,
        uint32_t opcode, uint32_t *data)
 {
        struct armv8_common *armv8 = dpm->arm->arch_info;
-       uint32_t dscr = DSCR_ITE;
        int retval;
 
        /* the opcode, writing data to DCC */
-       retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+       retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_read_dcc(armv8, data, &dscr);
+       return dpmv8_read_dcc(armv8, data, &dpm->dscr);
 }
 
 static int dpmv8_instr_read_data_dcc_64(struct arm_dpm *dpm,
        uint32_t opcode, uint64_t *data)
 {
        struct armv8_common *armv8 = dpm->arm->arch_info;
-       uint32_t dscr = DSCR_ITE;
        int retval;
 
        /* the opcode, writing data to DCC */
-       retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+       retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_read_dcc_64(armv8, data, &dscr);
+       return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
 }
 
 static int dpmv8_instr_read_data_r0(struct arm_dpm *dpm,
        uint32_t opcode, uint32_t *data)
 {
        struct armv8_common *armv8 = dpm->arm->arch_info;
-       uint32_t dscr = DSCR_ITE;
        int retval;
 
        /* the opcode, writing data to R0 */
-       retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+       retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
        if (retval != ERROR_OK)
                return retval;
 
        /* write R0 to DCC */
-       retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dscr);
+       retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dpm->dscr);
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_read_dcc(armv8, data, &dscr);
+       return dpmv8_read_dcc(armv8, data, &dpm->dscr);
 }
 
 static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm,
        uint32_t opcode, uint64_t *data)
 {
        struct armv8_common *armv8 = dpm->arm->arch_info;
-       uint32_t dscr = DSCR_ITE;
        int retval;
 
        /* the opcode, writing data to R0 */
-       retval = dpmv8_exec_opcode(dpm, opcode, &dscr);
+       retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
        if (retval != ERROR_OK)
                return retval;
 
        /* write R0 to DCC */
-       retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+       retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
        if (retval != ERROR_OK)
                return retval;
 
-       return dpmv8_read_dcc_64(armv8, data, &dscr);
+       return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
 }
 
 #if 0
@@ -1314,7 +1300,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr)
                        /* ?? */
                        break;
                default:
-                       LOG_DEBUG("Unknow core_state");
+                       LOG_DEBUG("Unknown core_state");
                        break;
        }
        dpm->wp_pc = addr;
@@ -1353,6 +1339,10 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm)
                return;
        }
 
+       /* Clear sticky error */
+       mem_ap_write_u32(armv8->debug_ap,
+               armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
+
        armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
        dspsr = dlr;
        armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);
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