static int cortex_a8_mmu(struct target *target, int *enabled);
static int cortex_a8_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys);
-static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache);
-static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache);
-static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
-
/*
* FIXME do topology discovery using the ROM; don't
#define swjdp_memoryap 0
#define swjdp_debugap 1
+/* restore cp15_control_reg at resume */
+static int cortex_a8_restore_cp15_control_reg(struct target* target)
+{
+ int retval = ERROR_OK;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+
+ if (cortex_a8->cp15_control_reg !=cortex_a8->cp15_control_reg_curr)
+ {
+ cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
+ //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg);
+ }
+ return retval;
+}
+
+/* check address before cortex_a8_apb read write access with mmu on
+ * remove apb predictible data abort */
+static int cortex_a8_check_address(struct target *target, uint32_t address)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ uint32_t os_border = armv7a->armv7a_mmu.os_border;
+ if ((address < os_border) &&
+ (armv7a->arm.core_mode == ARM_MODE_SVC)) {
+ LOG_ERROR("%x access in userspace and target in supervisor",address);
+ return ERROR_FAIL;
+ }
+ if ((address >= os_border) &&
+ (cortex_a8->curr_mode != ARM_MODE_SVC)) {
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+ cortex_a8->curr_mode = ARM_MODE_SVC;
+ LOG_INFO("%x access in kernel space and target not in supervisor",
+ address);
+ return ERROR_OK;
+ }
+ if ((address < os_border) &&
+ (cortex_a8->curr_mode == ARM_MODE_SVC)) {
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+ cortex_a8->curr_mode = ARM_MODE_ANY;
+ }
+ return ERROR_OK;
+}
+/* modify cp15_control_reg in order to enable or disable mmu for :
+ * - virt2phys address conversion
+ * - read or write memory in phys or virt address */
+static int cortex_a8_mmu_modify(struct target *target, int enable)
+{
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ int retval = ERROR_OK;
+ if (enable)
+ {
+ /* if mmu enabled at target stop and mmu not enable */
+ if (!(cortex_a8->cp15_control_reg & 0x1U))
+ {
+ LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
+ return ERROR_FAIL;
+ }
+ if (!(cortex_a8->cp15_control_reg_curr & 0x1U))
+ {
+ cortex_a8->cp15_control_reg_curr |= 0x1U;
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg_curr);
+ }
+ }
+ else
+ {
+ if (cortex_a8->cp15_control_reg_curr & 0x4U)
+ {
+ /* data cache is active */
+ cortex_a8->cp15_control_reg_curr &= ~0x4U;
+ /* flush data cache armv7 function to be called */
+ if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache)
+ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target);
+ }
+ if ( (cortex_a8->cp15_control_reg_curr & 0x1U))
+ {
+ cortex_a8->cp15_control_reg_curr &= ~0x1U;
+ retval = armv7a->arm.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cortex_a8->cp15_control_reg_curr);
+ }
+ }
+ return retval;
+}
+
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
*/
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
uint32_t dummy;
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
dscr = dscr_p ? *dscr_p : 0;
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
if (reg > 17)
return retval;
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value);
static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_sel_write_u32(a8->armv7a_common.armv4_5_common.dap,
+ return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap,
swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
uint32_t *dscr_p)
{
- struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap;
+ struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap;
+ struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
uint32_t dscr;
int retval;
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
return cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
}
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
/* then the opcode, taking data from R0 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
/* the opcode, writing data to DCC */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
/* the opcode, writing data to R0 */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
/* write R0 to DCC */
retval = cortex_a8_exec_opcode(
- a8->armv7a_common.armv4_5_common.target,
+ a8->armv7a_common.arm.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
struct arm_dpm *dpm = &a8->armv7a_common.dpm;
int retval;
- dpm->arm = &a8->armv7a_common.armv4_5_common;
+ dpm->arm = &a8->armv7a_common.arm;
dpm->didr = didr;
dpm->prepare = cortex_a8_dpm_prepare;
uint32_t dscr;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
enum target_state prev_target_state = target->state;
// toggle to another core is done by gdb as follow
// maint packet J core_id
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
/*
* Tell the core to be halted by writing DRCR with 0x1
uint32_t *address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *arm = &armv7a->arm;
int retval;
uint32_t resume_pc;
#endif
/* current = 1: continue on current pc, otherwise continue at <address> */
- resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
+ resume_pc = buf_get_u32(arm->pc->value, 0, 32);
if (!current)
resume_pc = *address;
else
/* Make sure that the Armv7 gdb thumb fixups does not
* kill the return address
*/
- switch (armv4_5->core_state)
+ switch (arm->core_state)
{
case ARM_STATE_ARM:
resume_pc &= 0xFFFFFFFC;
return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc);
- armv4_5->pc->dirty = 1;
- armv4_5->pc->valid = 1;
-
+ buf_set_u32(arm->pc->value, 0, 32, resume_pc);
+ arm->pc->dirty = 1;
+ arm->pc->valid = 1;
+ /* restore dpm_mode at system halt */
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+ /* called it now before restoring context because it uses cpu
+ * register r0 for restoring cp15 control register */
+ retval = cortex_a8_restore_cp15_control_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
retval = cortex_a8_restore_context(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
target->state = TARGET_RUNNING;
/* registers are now invalid */
- register_cache_invalidate(armv4_5->core_cache);
+ register_cache_invalidate(arm->core_cache);
#if 0
/* the front-end may request us not to handle breakpoints */
static int cortex_a8_internal_restart(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct adiv5_dap *swjdp = armv4_5->dap;
+ struct arm *arm = &armv7a->arm;
+ struct adiv5_dap *swjdp = arm->dap;
int retval;
uint32_t dscr;
/*
target->state = TARGET_RUNNING;
/* registers are now invalid */
- register_cache_invalidate(armv4_5->core_cache);
+ register_cache_invalidate(arm->core_cache);
return ERROR_OK;
}
cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
if (target->smp)
{ target->gdb_service->core[0] = -1;
- retval += cortex_a8_restore_smp(target, handle_breakpoints);
+ retval = cortex_a8_restore_smp(target, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
}
cortex_a8_internal_restart(target);
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct arm *arm = &armv7a->arm;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* read Current PSR */
retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ /* store current cpsr */
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- arm_set_cpsr(armv4_5, cpsr);
+ arm_set_cpsr(arm, cpsr);
/* update cache */
for (i = 0; i <= ARM_PC; i++)
{
- reg = arm_reg_current(armv4_5, i);
+ reg = arm_reg_current(arm, i);
buf_set_u32(reg->value, 0, 32, regfile[i]);
reg->valid = 1;
regfile[ARM_PC] -= 8;
}
- reg = armv4_5->pc;
+ reg = arm->pc;
buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
reg->dirty = reg->valid;
}
int retval;
/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
+ retval = armv7a->arm.mrc(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cortex_a8->cp15_control_reg);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
+ cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
- if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
+ if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1)
{
- uint32_t cache_type_reg;
-
- /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 1, /* op1, op2 */
- 0, 0, /* CRn, CRm */
- &cache_type_reg);
- if (retval != ERROR_OK)
- return retval;
- LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
-
- /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
- armv4_5_identify_cache(cache_type_reg,
- &armv7a->armv4_5_mmu.armv4_5_cache);
+ armv7a_identify_cache(target);
}
- armv7a->armv4_5_mmu.mmu_enabled =
+ armv7a->armv7a_mmu.mmu_enabled =
(cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
- armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+ armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
(cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
- armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
+ armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled =
(cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
+ cortex_a8->curr_mode = armv7a->arm.core_mode;
return ERROR_OK;
}
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *arm = &armv7a->arm;
struct breakpoint *breakpoint = NULL;
struct breakpoint stepbreakpoint;
struct reg *r;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
- r = armv4_5->pc;
+ r = arm->pc;
if (!current)
{
buf_set_u32(r->value, 0, 32, address);
/* Setup single step breakpoint */
stepbreakpoint.address = address;
- stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB)
+ stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB)
? 2 : 4;
stepbreakpoint.type = BKPT_HARD;
stepbreakpoint.set = 0;
}
/* registers are now invalid */
- register_cache_invalidate(armv7a->armv4_5_common.core_cache);
+ register_cache_invalidate(armv7a->arm.core_cache);
target->state = TARGET_RESET;
/* write memory through APB-AP */
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *arm = &armv7a->arm;
int total_bytes = count * size;
int start_byte, nbytes_to_write, i;
struct reg *reg;
return ERROR_TARGET_NOT_HALTED;
}
- reg = arm_reg_current(armv4_5, 0);
+ reg = arm_reg_current(arm, 0);
reg->dirty = 1;
- reg = arm_reg_current(armv4_5, 1);
+ reg = arm_reg_current(arm, 1);
reg->dirty = 1;
retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0);
/* read memory through APB-AP */
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *arm = &armv7a->arm;
int total_bytes = count * size;
int start_byte, nbytes_to_read, i;
struct reg *reg;
return ERROR_TARGET_NOT_HALTED;
}
- reg = arm_reg_current(armv4_5, 0);
+ reg = arm_reg_current(arm, 0);
reg->dirty = 1;
- reg = arm_reg_current(armv4_5, 1);
+ reg = arm_reg_current(arm, 1);
reg->dirty = 1;
retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0);
uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
- int retval = ERROR_INVALID_ARGUMENTS;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d",
address, size, count);
} else {
/* read memory through APB-AP */
- int enabled = 0;
-
- retval = cortex_a8_mmu(target, &enabled);
- if (retval != ERROR_OK)
- return retval;
-
- if (enabled)
- {
- LOG_WARNING("Reading physical memory through \
- APB with MMU enabled is not yet implemented");
- return ERROR_TARGET_FAILURE;
- }
+ /* disable mmu */
+ retval = cortex_a8_mmu_modify(target, 0);
+ if (retval != ERROR_OK) return retval;
retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer);
}
}
uint32_t virt, phys;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
/* cortex_a8 handles unaligned memory access */
}
retval = cortex_a8_read_phys_memory(target, address, size, count, buffer);
} else {
+ retval = cortex_a8_check_address(target, address);
+ if (retval != ERROR_OK) return retval;
+ /* enable mmu */
+ retval = cortex_a8_mmu_modify(target, 1);
+ if (retval != ERROR_OK) return retval;
retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer);
}
return retval;
uint32_t count, const uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
- int retval = ERROR_INVALID_ARGUMENTS;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address,
} else {
/* write memory through APB-AP */
- int enabled = 0;
-
- retval = cortex_a8_mmu(target, &enabled);
+ retval = cortex_a8_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
-
- if (enabled)
- {
- LOG_WARNING("Writing physical memory through APB with MMU" \
- "enabled is not yet implemented");
- return ERROR_TARGET_FAILURE;
- }
- return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
+ return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
}
}
/* REVISIT this op is generic ARMv7-A/R stuff */
if (retval == ERROR_OK && target->state == TARGET_HALTED)
{
- struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
+ struct arm_dpm *dpm = armv7a->arm.dpm;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
*/
/* invalidate I-Cache */
- if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+ if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled)
{
/* ICIMVAU - Invalidate Cache single entry
* with MVA to PoU
}
/* invalidate D-Cache */
- if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+ if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled)
{
/* DCIMVAC - Invalidate data Cache line
* with MVA to PoC
uint32_t virt, phys;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
/* cortex_a8 handles unaligned memory access */
LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address,
count, buffer);
}
else {
+ retval = cortex_a8_check_address(target, address);
+ if (retval != ERROR_OK) return retval;
+ /* enable mmu */
+ retval = cortex_a8_mmu_modify(target, 1);
+ if (retval != ERROR_OK) return retval;
retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
}
return retval;
{
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
if (!target_was_examined(target))
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
int i;
int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
LOG_DEBUG("didr = 0x%08" PRIx32, didr);
- armv7a->armv4_5_common.core_type = ARM_MODE_MON;
+ armv7a->arm.core_type = ARM_MODE_MON;
retval = cortex_a8_dpm_setup(cortex_a8, didr);
if (retval != ERROR_OK)
return retval;
struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct arm *armv4_5 = &armv7a->armv4_5_common;
struct adiv5_dap *dap = &armv7a->dap;
- armv7a->armv4_5_common.dap = dap;
+ armv7a->arm.dap = dap;
/* Setup struct cortex_a8_common */
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
/* tap has no dap initialized */
if (!tap->dap)
{
- armv7a->armv4_5_common.dap = dap;
+ armv7a->arm.dap = dap;
/* Setup struct cortex_a8_common */
- armv4_5->arch_info = armv7a;
/* prepare JTAG information for the new target */
cortex_a8->jtag_info.tap = tap;
tap->dap = dap;
}
else
- armv7a->armv4_5_common.dap = tap->dap;
+ armv7a->arm.dap = tap->dap;
cortex_a8->fast_reg_read = 0;
- /* Set default value */
- cortex_a8->current_address_mode = ARM_MODE_ANY;
-
/* register arch-specific functions */
armv7a->examine_debug_reason = NULL;
armv7a->post_debug_entry = cortex_a8_post_debug_entry;
armv7a->pre_restore_context = NULL;
- armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
- armv7a->armv4_5_mmu.get_ttb = cortex_a8_get_ttb;
- armv7a->armv4_5_mmu.read_memory = cortex_a8_read_phys_memory;
- armv7a->armv4_5_mmu.write_memory = cortex_a8_write_phys_memory;
- armv7a->armv4_5_mmu.disable_mmu_caches = cortex_a8_disable_mmu_caches;
- armv7a->armv4_5_mmu.enable_mmu_caches = cortex_a8_enable_mmu_caches;
- armv7a->armv4_5_mmu.has_tiny_pages = 1;
- armv7a->armv4_5_mmu.mmu_enabled = 0;
+ armv7a->armv7a_mmu.read_physical_memory = cortex_a8_read_phys_memory;
+
// arm7_9->handle_target_request = cortex_a8_handle_target_request;
/* REVISIT v7a setup should be in a v7a-specific routine */
- arm_init_arch_info(target, armv4_5);
- armv7a->common_magic = ARMV7_COMMON_MAGIC;
-
+ armv7a_init_arch_info(target, armv7a);
target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
return ERROR_OK;
return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
}
-static int cortex_a8_get_ttb(struct target *target, uint32_t *result)
-{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- uint32_t ttb = 0, retval = ERROR_OK;
-
- /* current_address_mode is set inside cortex_a8_virt2phys()
- where we can determine if address belongs to user or kernel */
- if(cortex_a8->current_address_mode == ARM_MODE_SVC)
- {
- /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 1, /* op1, op2 */
- 2, 0, /* CRn, CRm */
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- }
- else if(cortex_a8->current_address_mode == ARM_MODE_USR)
- {
- /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 0, /* op1, op2 */
- 2, 0, /* CRn, CRm */
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- }
- /* we don't know whose address is: user or kernel
- we assume that if we are in kernel mode then
- address belongs to kernel else if in user mode
- - to user */
- else if(armv7a->armv4_5_common.core_mode == ARM_MODE_SVC)
- {
- /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 1, /* op1, op2 */
- 2, 0, /* CRn, CRm */
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- }
- else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR)
- {
- /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 0, /* op1, op2 */
- 2, 0, /* CRn, CRm */
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- }
- /* finally we don't know whose ttb to use: user or kernel */
- else
- LOG_ERROR("Don't know how to get ttb for current mode!!!");
-
- ttb &= 0xffffc000;
-
- *result = ttb;
-
- return ERROR_OK;
-}
-
-static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache)
-{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- uint32_t cp15_control;
- int retval;
-
- /* read cp15 control register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- &cp15_control);
- if (retval != ERROR_OK)
- return retval;
-
-
- if (mmu)
- cp15_control &= ~0x1U;
-
- if (d_u_cache)
- cp15_control &= ~0x4U;
-
- if (i_cache)
- cp15_control &= ~0x1000U;
-
- retval = armv7a->armv4_5_common.mcr(target, 15,
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- cp15_control);
- return retval;
-}
-
-static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
- int d_u_cache, int i_cache)
-{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- uint32_t cp15_control;
- int retval;
-
- /* read cp15 control register */
- retval = armv7a->armv4_5_common.mrc(target, 15,
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- &cp15_control);
- if (retval != ERROR_OK)
- return retval;
-
- if (mmu)
- cp15_control |= 0x1U;
-
- if (d_u_cache)
- cp15_control |= 0x4U;
-
- if (i_cache)
- cp15_control |= 0x1000U;
-
- retval = armv7a->armv4_5_common.mcr(target, 15,
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- cp15_control);
- return retval;
-}
static int cortex_a8_mmu(struct target *target, int *enabled)
return ERROR_TARGET_INVALID;
}
- *enabled = target_to_cortex_a8(target)->armv7a_common.armv4_5_mmu.mmu_enabled;
+ *enabled = target_to_cortex_a8(target)->armv7a_common.armv7a_mmu.mmu_enabled;
return ERROR_OK;
}
static int cortex_a8_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys)
{
- uint32_t cb;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- // struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ int retval = ERROR_FAIL;
struct armv7a_common *armv7a = target_to_armv7a(target);
-
- /* We assume that virtual address is separated
- between user and kernel in Linux style:
- 0x00000000-0xbfffffff - User space
- 0xc0000000-0xffffffff - Kernel space */
- if( virt < 0xc0000000 ) /* Linux user space */
- cortex_a8->current_address_mode = ARM_MODE_USR;
- else /* Linux kernel */
- cortex_a8->current_address_mode = ARM_MODE_SVC;
- uint32_t ret;
- int retval = armv4_5_mmu_translate_va(target,
- &armv7a->armv4_5_mmu, virt, &cb, &ret);
- if (retval != ERROR_OK)
- return retval;
- /* Reset the flag. We don't want someone else to use it by error */
- cortex_a8->current_address_mode = ARM_MODE_ANY;
-
- *phys = ret;
- return ERROR_OK;
+ struct adiv5_dap *swjdp = armv7a->arm.dap;
+ uint8_t apsel = swjdp->apsel;
+ if (apsel == swjdp_memoryap)
+ {
+ uint32_t ret;
+ retval = armv7a_mmu_translate_va(target,
+ virt, &ret);
+ if (retval != ERROR_OK)
+ goto done;
+ *phys = ret;
+ }
+ else
+ { /* use this method if swjdp_memoryap not selected */
+ /* mmu must be enable in order to get a correct translation */
+ retval = cortex_a8_mmu_modify(target, 1);
+ if (retval != ERROR_OK) goto done;
+ retval = armv7a_mmu_translate_va_pa(target, virt, phys, 1);
+ }
+done:
+ return retval;
}
COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- return armv4_5_handle_cache_info_command(CMD_CTX,
- &armv7a->armv4_5_mmu.armv4_5_cache);
+ return armv7a_handle_cache_info_command(CMD_CTX,
+ &armv7a->armv7a_mmu.armv7a_cache);
}
.handler = cortex_a8_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about target caches",
+ .usage = "",
},
{
.name = "dbginit",
.handler = cortex_a8_handle_dbginit_command,
.mode = COMMAND_EXEC,
.help = "Initialize core debug",
+ .usage = "",
},
{ .name ="smp_off",
.handler = cortex_a8_handle_smp_off_command,
.mode = COMMAND_EXEC,
.help = "Stop smp handling",
+ .usage = "",
},
{
.name ="smp_on",
.handler = cortex_a8_handle_smp_on_command,
.mode = COMMAND_EXEC,
.help = "Restart smp handling",
+ .usage = "",
},
{
.name ="smp_gdb",
.handler = cortex_a8_handle_smp_gdb_command,
.mode = COMMAND_EXEC,
.help = "display/fix current core played to gdb",
+ .usage = "",
},
.name = "cortex_a8",
.mode = COMMAND_ANY,
.help = "Cortex-A8 command group",
+ .usage = "",
.chain = cortex_a8_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
.write_phys_memory = cortex_a8_write_phys_memory,
.mmu = cortex_a8_mmu,
.virt2phys = cortex_a8_virt2phys,
-
};
Code Review / openocd.git / blobdiff