arm_coresight: add include file and use it

[openocd.git] / src / target / cortex_a.c

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 9a48cc8b1b93a8ac449dc924a7e45ffe0e639df6..bf65544f51afa133d33a458ccd51c4adcbc5c6d4 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -56,6 +56,7 @@
 #include "armv7a_mmu.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_coresight.h"
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
 #include "jtag/interface.h"
@@ -641,7 +642,7 @@ static struct target *get_cortex_a(struct target *target, int32_t coreid)
        struct target *curr;
 
        head = target->head;
-       while (head != (struct target_list *)NULL) {
+       while (head) {
                curr = head->target;
                if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
                        return curr;
@@ -657,7 +658,7 @@ static int cortex_a_halt_smp(struct target *target)
        struct target_list *head;
        struct target *curr;
        head = target->head;
-       while (head != (struct target_list *)NULL) {
+       while (head) {
                curr = head->target;
                if ((curr != target) && (curr->state != TARGET_HALTED)
                        && target_was_examined(curr))
@@ -704,7 +705,7 @@ static int update_halt_gdb(struct target *target)
        }
 
        /* after all targets were updated, poll the gdb serving target */
-       if (gdb_target != NULL && gdb_target != target)
+       if (gdb_target && gdb_target != target)
                cortex_a_poll(gdb_target);
        return retval;
 }
@@ -726,7 +727,7 @@ static int cortex_a_poll(struct target *target)
        /*  the next polling trigger an halt event sent to gdb */
        if ((target->state == TARGET_HALTED) && (target->smp) &&
                (target->gdb_service) &&
-               (target->gdb_service->target == NULL)) {
+               (!target->gdb_service->target)) {
                target->gdb_service->target =
                        get_cortex_a(target, target->gdb_service->core[1]);
                target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -953,7 +954,7 @@ static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
        struct target *curr;
        target_addr_t address;
        head = target->head;
-       while (head != (struct target_list *)NULL) {
+       while (head) {
                curr = head->target;
                if ((curr != target) && (curr->state != TARGET_RUNNING)
                        && target_was_examined(curr)) {
@@ -1138,7 +1139,7 @@ static int cortex_a_set_dscr_bits(struct target *target,
        /* Read DSCR */
        int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
-       if (ERROR_OK != retval)
+       if (retval != ERROR_OK)
                return retval;
 
        /* clear bitfield */
@@ -1197,7 +1198,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
        /* Disable interrupts during single step if requested */
        if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
                retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, DSCR_INT_DIS);
-               if (ERROR_OK != retval)
+               if (retval != ERROR_OK)
                        return retval;
        }
 
@@ -1228,7 +1229,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
        /* Re-enable interrupts if they were disabled */
        if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
                retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, 0);
-               if (ERROR_OK != retval)
+               if (retval != ERROR_OK)
                        return retval;
        }
 
@@ -1290,16 +1291,16 @@ static int cortex_a_set_breakpoint(struct target *target,
                control = ((matchmode & 0x7) << 20)
                        | (byte_addr_select << 5)
                        | (3 << 1) | 1;
-               brp_list[brp_i].used = 1;
+               brp_list[brp_i].used = true;
                brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
                brp_list[brp_i].control = control;
                retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                               + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+                               + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
                                brp_list[brp_i].value);
                if (retval != ERROR_OK)
                        return retval;
                retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                               + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+                               + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
                                brp_list[brp_i].control);
                if (retval != ERROR_OK)
                        return retval;
@@ -1384,16 +1385,16 @@ static int cortex_a_set_context_breakpoint(struct target *target,
        control = ((matchmode & 0x7) << 20)
                | (byte_addr_select << 5)
                | (3 << 1) | 1;
-       brp_list[brp_i].used = 1;
+       brp_list[brp_i].used = true;
        brp_list[brp_i].value = (breakpoint->asid);
        brp_list[brp_i].control = control;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
                        brp_list[brp_i].value);
        if (retval != ERROR_OK)
                return retval;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
                        brp_list[brp_i].control);
        if (retval != ERROR_OK)
                return retval;
@@ -1409,11 +1410,11 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
        int retval = ERROR_FAIL;
        int brp_1 = 0;  /* holds the contextID pair */
        int brp_2 = 0;  /* holds the IVA pair */
-       uint32_t control_CTX, control_IVA;
-       uint8_t CTX_byte_addr_select = 0x0F;
-       uint8_t IVA_byte_addr_select = 0x0F;
-       uint8_t CTX_machmode = 0x03;
-       uint8_t IVA_machmode = 0x01;
+       uint32_t control_ctx, control_iva;
+       uint8_t ctx_byte_addr_select = 0x0F;
+       uint8_t iva_byte_addr_select = 0x0F;
+       uint8_t ctx_machmode = 0x03;
+       uint8_t iva_machmode = 0x01;
        struct cortex_a_common *cortex_a = target_to_cortex_a(target);
        struct armv7a_common *armv7a = &cortex_a->armv7a_common;
        struct cortex_a_brp *brp_list = cortex_a->brp_list;
@@ -1427,7 +1428,7 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
                (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num))
                brp_1++;
 
-       printf("brp(CTX) found num: %d\n", brp_1);
+       LOG_DEBUG("brp(CTX) found num: %d", brp_1);
        if (brp_1 >= cortex_a->brp_num) {
                LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
                return ERROR_FAIL;
@@ -1437,47 +1438,47 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
                (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a->brp_num))
                brp_2++;
 
-       printf("brp(IVA) found num: %d\n", brp_2);
+       LOG_DEBUG("brp(IVA) found num: %d", brp_2);
        if (brp_2 >= cortex_a->brp_num) {
                LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
                return ERROR_FAIL;
        }
 
        breakpoint->set = brp_1 + 1;
-       breakpoint->linked_BRP = brp_2;
-       control_CTX = ((CTX_machmode & 0x7) << 20)
+       breakpoint->linked_brp = brp_2;
+       control_ctx = ((ctx_machmode & 0x7) << 20)
                | (brp_2 << 16)
                | (0 << 14)
-               | (CTX_byte_addr_select << 5)
+               | (ctx_byte_addr_select << 5)
                | (3 << 1) | 1;
-       brp_list[brp_1].used = 1;
+       brp_list[brp_1].used = true;
        brp_list[brp_1].value = (breakpoint->asid);
-       brp_list[brp_1].control = control_CTX;
+       brp_list[brp_1].control = control_ctx;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
+                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn,
                        brp_list[brp_1].value);
        if (retval != ERROR_OK)
                return retval;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
+                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn,
                        brp_list[brp_1].control);
        if (retval != ERROR_OK)
                return retval;
 
-       control_IVA = ((IVA_machmode & 0x7) << 20)
+       control_iva = ((iva_machmode & 0x7) << 20)
                | (brp_1 << 16)
-               | (IVA_byte_addr_select << 5)
+               | (iva_byte_addr_select << 5)
                | (3 << 1) | 1;
-       brp_list[brp_2].used = 1;
+       brp_list[brp_2].used = true;
        brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
-       brp_list[brp_2].control = control_IVA;
+       brp_list[brp_2].control = control_iva;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
+                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn,
                        brp_list[brp_2].value);
        if (retval != ERROR_OK)
                return retval;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
+                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn,
                        brp_list[brp_2].control);
        if (retval != ERROR_OK)
                return retval;
@@ -1500,23 +1501,23 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
        if (breakpoint->type == BKPT_HARD) {
                if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
                        int brp_i = breakpoint->set - 1;
-                       int brp_j = breakpoint->linked_BRP;
+                       int brp_j = breakpoint->linked_brp;
                        if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
                                LOG_DEBUG("Invalid BRP number in breakpoint");
                                return ERROR_OK;
                        }
                        LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
                                brp_list[brp_i].control, brp_list[brp_i].value);
-                       brp_list[brp_i].used = 0;
+                       brp_list[brp_i].used = false;
                        brp_list[brp_i].value = 0;
                        brp_list[brp_i].control = 0;
                        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+                                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
                                        brp_list[brp_i].control);
                        if (retval != ERROR_OK)
                                return retval;
                        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+                                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
                                        brp_list[brp_i].value);
                        if (retval != ERROR_OK)
                                return retval;
@@ -1526,20 +1527,20 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
                        }
                        LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
                                brp_list[brp_j].control, brp_list[brp_j].value);
-                       brp_list[brp_j].used = 0;
+                       brp_list[brp_j].used = false;
                        brp_list[brp_j].value = 0;
                        brp_list[brp_j].control = 0;
                        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn,
+                                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn,
                                        brp_list[brp_j].control);
                        if (retval != ERROR_OK)
                                return retval;
                        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn,
+                                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn,
                                        brp_list[brp_j].value);
                        if (retval != ERROR_OK)
                                return retval;
-                       breakpoint->linked_BRP = 0;
+                       breakpoint->linked_brp = 0;
                        breakpoint->set = 0;
                        return ERROR_OK;
 
@@ -1551,16 +1552,16 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
                        }
                        LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
                                brp_list[brp_i].control, brp_list[brp_i].value);
-                       brp_list[brp_i].used = 0;
+                       brp_list[brp_i].used = false;
                        brp_list[brp_i].value = 0;
                        brp_list[brp_i].control = 0;
                        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+                                       + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
                                        brp_list[brp_i].control);
                        if (retval != ERROR_OK)
                                return retval;
                        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+                                       + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
                                        brp_list[brp_i].value);
                        if (retval != ERROR_OK)
                                return retval;
@@ -1753,18 +1754,18 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
                (byte_address_select << 5) |
                (load_store_access_control << 3) |
                (0x3 << 1) | 1;
-       wrp_list[wrp_i].used = 1;
+       wrp_list[wrp_i].used = true;
        wrp_list[wrp_i].value = address;
        wrp_list[wrp_i].control = control;
 
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].WRPn,
+                       + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
                        wrp_list[wrp_i].value);
        if (retval != ERROR_OK)
                return retval;
 
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].WRPn,
+                       + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
                        wrp_list[wrp_i].control);
        if (retval != ERROR_OK)
                return retval;
@@ -1803,16 +1804,16 @@ static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *w
        }
        LOG_DEBUG("wrp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
                        wrp_list[wrp_i].control, wrp_list[wrp_i].value);
-       wrp_list[wrp_i].used = 0;
+       wrp_list[wrp_i].used = false;
        wrp_list[wrp_i].value = 0;
        wrp_list[wrp_i].control = 0;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].WRPn,
+                       + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
                        wrp_list[wrp_i].control);
        if (retval != ERROR_OK)
                return retval;
        retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-                       + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].WRPn,
+                       + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
                        wrp_list[wrp_i].value);
        if (retval != ERROR_OK)
                return retval;
@@ -2886,16 +2887,21 @@ static int cortex_a_examine_first(struct target *target)
        struct cortex_a_common *cortex_a = target_to_cortex_a(target);
        struct armv7a_common *armv7a = &cortex_a->armv7a_common;
        struct adiv5_dap *swjdp = armv7a->arm.dap;
+       struct adiv5_private_config *pc = target->private_config;
 
        int i;
        int retval = ERROR_OK;
        uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
 
-       /* Search for the APB-AP - it is needed for access to debug registers */
-       retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
-       if (retval != ERROR_OK) {
-               LOG_ERROR("Could not find APB-AP for debug access");
-               return retval;
+       if (pc->ap_num == DP_APSEL_INVALID) {
+               /* Search for the APB-AP - it is needed for access to debug registers */
+               retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
+               if (retval != ERROR_OK) {
+                       LOG_ERROR("Could not find APB-AP for debug access");
+                       return retval;
+               }
+       } else {
+               armv7a->debug_ap = dap_ap(swjdp, pc->ap_num);
        }
 
        retval = mem_ap_init(armv7a->debug_ap);
@@ -2907,7 +2913,7 @@ static int cortex_a_examine_first(struct target *target)
        armv7a->debug_ap->memaccess_tck = 80;
 
        if (!target->dbgbase_set) {
-               uint32_t dbgbase;
+               target_addr_t dbgbase;
                /* Get ROM Table base */
                uint32_t apid;
                int32_t coreidx = target->coreid;
@@ -2916,15 +2922,15 @@ static int cortex_a_examine_first(struct target *target)
                retval = dap_get_debugbase(armv7a->debug_ap, &dbgbase, &apid);
                if (retval != ERROR_OK)
                        return retval;
-               /* Lookup 0x15 -- Processor DAP */
-               retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, 0x15,
+               /* Lookup Processor DAP */
+               retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
                                &armv7a->debug_base, &coreidx);
                if (retval != ERROR_OK) {
                        LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
                                  target->cmd_name);
                        return retval;
                }
-               LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
+               LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
                          target->coreid, armv7a->debug_base);
        } else
                armv7a->debug_base = target->dbgbase;
@@ -3033,14 +3039,14 @@ static int cortex_a_examine_first(struct target *target)
        cortex_a->brp_list = calloc(cortex_a->brp_num, sizeof(struct cortex_a_brp));
 /*     cortex_a->brb_enabled = ????; */
        for (i = 0; i < cortex_a->brp_num; i++) {
-               cortex_a->brp_list[i].used = 0;
+               cortex_a->brp_list[i].used = false;
                if (i < (cortex_a->brp_num-cortex_a->brp_num_context))
                        cortex_a->brp_list[i].type = BRP_NORMAL;
                else
                        cortex_a->brp_list[i].type = BRP_CONTEXT;
                cortex_a->brp_list[i].value = 0;
                cortex_a->brp_list[i].control = 0;
-               cortex_a->brp_list[i].BRPn = i;
+               cortex_a->brp_list[i].brpn = i;
        }
 
        LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
@@ -3051,10 +3057,10 @@ static int cortex_a_examine_first(struct target *target)
        free(cortex_a->wrp_list);
        cortex_a->wrp_list = calloc(cortex_a->wrp_num, sizeof(struct cortex_a_wrp));
        for (i = 0; i < cortex_a->wrp_num; i++) {
-               cortex_a->wrp_list[i].used = 0;
+               cortex_a->wrp_list[i].used = false;
                cortex_a->wrp_list[i].value = 0;
                cortex_a->wrp_list[i].control = 0;
-               cortex_a->wrp_list[i].WRPn = i;
+               cortex_a->wrp_list[i].wrpn = i;
        }
 
        LOG_DEBUG("Configured %i hw watchpoints", cortex_a->wrp_num);
@@ -3126,13 +3132,13 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
        struct cortex_a_common *cortex_a;
        struct adiv5_private_config *pc;
 
-       if (target->private_config == NULL)
+       if (!target->private_config)
                return ERROR_FAIL;
 
        pc = (struct adiv5_private_config *)target->private_config;
 
        cortex_a = calloc(1, sizeof(struct cortex_a_common));
-       if (cortex_a == NULL) {
+       if (!cortex_a) {
                LOG_ERROR("Out of memory");
                return ERROR_FAIL;
        }
@@ -3153,7 +3159,7 @@ static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
                return ERROR_FAIL;
 
        cortex_a = calloc(1, sizeof(struct cortex_a_common));
-       if (cortex_a == NULL) {
+       if (!cortex_a) {
                LOG_ERROR("Out of memory");
                return ERROR_FAIL;
        }
@@ -3181,6 +3187,7 @@ static void cortex_a_deinit_target(struct target *target)
                                        dscr & ~DSCR_HALT_DBG_MODE);
        }
 
+       free(cortex_a->wrp_list);
        free(cortex_a->brp_list);
        arm_free_reg_cache(dpm->arm);
        free(dpm->dbp);
@@ -3258,16 +3265,16 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
        struct target *target = get_current_target(CMD_CTX);
        struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 
-       static const Jim_Nvp nvp_maskisr_modes[] = {
+       static const struct jim_nvp nvp_maskisr_modes[] = {
                { .name = "off", .value = CORTEX_A_ISRMASK_OFF },
                { .name = "on", .value = CORTEX_A_ISRMASK_ON },
                { .name = NULL, .value = -1 },
        };
-       const Jim_Nvp *n;
+       const struct jim_nvp *n;
 
        if (CMD_ARGC > 0) {
-               n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
-               if (n->name == NULL) {
+               n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
+               if (!n->name) {
                        LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
                        return ERROR_COMMAND_SYNTAX_ERROR;
                }
@@ -3275,7 +3282,7 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
                cortex_a->isrmasking_mode = n->value;
        }
 
-       n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode);
+       n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode);
        command_print(CMD, "cortex_a interrupt mask %s", n->name);
 
        return ERROR_OK;
@@ -3286,22 +3293,22 @@ COMMAND_HANDLER(handle_cortex_a_dacrfixup_command)
        struct target *target = get_current_target(CMD_CTX);
        struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 
-       static const Jim_Nvp nvp_dacrfixup_modes[] = {
+       static const struct jim_nvp nvp_dacrfixup_modes[] = {
                { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF },
                { .name = "on", .value = CORTEX_A_DACRFIXUP_ON },
                { .name = NULL, .value = -1 },
        };
-       const Jim_Nvp *n;
+       const struct jim_nvp *n;
 
        if (CMD_ARGC > 0) {
-               n = Jim_Nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]);
-               if (n->name == NULL)
+               n = jim_nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]);
+               if (!n->name)
                        return ERROR_COMMAND_SYNTAX_ERROR;
                cortex_a->dacrfixup_mode = n->value;
 
        }
 
-       n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
+       n = jim_nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
        command_print(CMD, "cortex_a domain access control fixup %s", n->name);
 
        return ERROR_OK;