Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
Cortex-A8: better context restore
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 586b9ea605bb172efae15acff09cb536a8fd7b88..168fe127ddb68b960bce21dcd50d9964be835397 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -33,10 +33,9 @@
 #include "config.h"
 #endif
 
+#include "breakpoints.h"
 #include "cortex_a8.h"
-#include "armv7a.h"
-#include "armv4_5.h"
-
+#include "register.h"
 #include "target_request.h"
 #include "target_type.h"
 
@@ -238,22 +237,26 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
-       if (reg > 16)
+       if (reg > 17)
                return retval;
 
        if (reg < 15)
        {
-               /* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+               /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
        }
        else if (reg == 15)
        {
+               /* "MOV r0, r15"; then move r0 to DCCTX */
                cortex_a8_exec_opcode(target, 0xE1A0000F);
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
-       else if (reg == 16)
+       else
        {
-               cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
+               /* "MRS r0, CPSR" or "MRS r0, SPSR"
+                * then move r0 to DCCTX
+                */
+               cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1));
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
 
@@ -267,11 +270,13 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 
        retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DTRTX, value);
+       LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
 
        return retval;
 }
 
-static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+               uint32_t value, int regnum)
 {
        int retval = ERROR_OK;
        uint8_t Rd = regnum&0xFF;
@@ -291,29 +296,39 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t
                cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
        }
 
-       if (Rd > 16)
+       if (Rd > 17)
                return retval;
 
        /* Write to DCCRX */
+       LOG_DEBUG("write DCC 0x%08" PRIx32, value);
        retval = mem_ap_write_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DTRRX, value);
 
        if (Rd < 15)
        {
-               /* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+               /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
                cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
        }
        else if (Rd == 15)
        {
+               /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+                * then "mov r15, r0"
+                */
                cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
                cortex_a8_exec_opcode(target, 0xE1A0F000);
        }
-       else if (Rd == 16)
+       else
        {
+               /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+                * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
+                */
                cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-               cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
-               /* Execute a PrefetchFlush instruction through the ITR. */
-               cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+               cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1));
+
+               /* "Prefetch flush" after modifying execution status in CPSR */
+               if (Rd == 16)
+                       cortex_a8_exec_opcode(target,
+                                       ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
        }
 
        return retval;
@@ -481,7 +496,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        resume_pc = buf_get_u32(
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
                        0, 32);
        if (!current)
@@ -490,28 +505,33 @@ static int cortex_a8_resume(struct target *target, int current,
        /* Make sure that the Armv7 gdb thumb fixups does not
         * kill the return address
         */
-       if (armv7a->core_state == ARMV7A_STATE_ARM)
+       switch (armv4_5->core_state)
        {
+       case ARMV4_5_STATE_ARM:
                resume_pc &= 0xFFFFFFFC;
-       }
-       /* When the return address is loaded into PC
-        * bit 0 must be 1 to stay in Thumb state
-        */
-       if (armv7a->core_state == ARMV7A_STATE_THUMB)
-       {
+               break;
+       case ARMV4_5_STATE_THUMB:
+       case ARM_STATE_THUMB_EE:
+               /* When the return address is loaded into PC
+                * bit 0 must be 1 to stay in Thumb state
+                */
                resume_pc |= 0x1;
+               break;
+       case ARMV4_5_STATE_JAZELLE:
+               LOG_ERROR("How do I resume into Jazelle state??");
+               return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
                        0, 32, resume_pc);
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        armv4_5->core_mode, 15).dirty = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        armv4_5->core_mode, 15).valid = 1;
 
        cortex_a8_restore_context(target);
-//     arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+
 #if 0
        /* the front-end may request us not to handle breakpoints */
        if (handle_breakpoints)
@@ -539,7 +559,7 @@ static int cortex_a8_resume(struct target *target, int current,
        target->state = TARGET_RUNNING;
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv4_5->core_cache);
 
        if (!debug_execution)
        {
@@ -569,6 +589,7 @@ static int cortex_a8_debug_entry(struct target *target)
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
+       struct reg *reg;
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
@@ -605,6 +626,9 @@ static int cortex_a8_debug_entry(struct target *target)
        /* First load register acessible through core debug port*/
        if (!regfile_working_area)
        {
+               /* FIXME we don't actually need all these registers;
+                * reading them slows us down.  Just R0, PC, CPSR...
+                */
                for (i = 0; i <= 15; i++)
                        cortex_a8_dap_read_coreregister_u32(target,
                                        &regfile[i], i);
@@ -618,32 +642,55 @@ static int cortex_a8_debug_entry(struct target *target)
                target_free_working_area(target, regfile_working_area);
        }
 
+       /* read Current PSR */
        cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
        pc = regfile[15];
        dap_ap_select(swjdp, swjdp_debugap);
        LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
        armv4_5->core_mode = cpsr & 0x1F;
-       armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
+
+       i = (cpsr >> 5) & 1;    /* T */
+       i |= (cpsr >> 23) & 1;  /* J << 1 */
+       switch (i) {
+       case 0: /* J = 0, T = 0 */
+               armv4_5->core_state = ARMV4_5_STATE_ARM;
+               break;
+       case 1: /* J = 0, T = 1 */
+               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               break;
+       case 2: /* J = 1, T = 0 */
+               LOG_WARNING("Jazelle state -- not handled");
+               armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+               break;
+       case 3: /* J = 1, T = 1 */
+               /* ThumbEE is very much like Thumb, but some of the
+                * instructions are different.  Single stepping and
+                * breakpoints need updating...
+                */
+               LOG_WARNING("ThumbEE -- incomplete support");
+               armv4_5->core_state = ARM_STATE_THUMB_EE;
+               break;
+       }
+
+       /* update cache */
+       reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
+       buf_set_u32(reg->value, 0, 32, cpsr);
+       reg->valid = 1;
+       reg->dirty = 0;
 
        for (i = 0; i <= ARM_PC; i++)
        {
-               buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                                       armv4_5->core_mode, i).value,
-                               0, 32, regfile[i]);
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, i).valid = 1;
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, i).dirty = 0;
-       }
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 16).value,
-                       0, 32, cpsr);
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
+               reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+                                       armv4_5->core_mode, i);
+
+               buf_set_u32(reg->value, 0, 32, regfile[i]);
+               reg->valid = 1;
+               reg->dirty = 0;
+       }
 
        /* Fixup PC Resume Address */
-       if (armv7a->core_state == ARMV7A_STATE_THUMB)
+       if (cpsr & (1 << 5))
        {
                // T bit set for Thumb or ThumbEE state
                regfile[ARM_PC] -= 4;
@@ -653,15 +700,15 @@ static int cortex_a8_debug_entry(struct target *target)
                // ARM state
                regfile[ARM_PC] -= 8;
        }
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, ARM_PC).value,
                        0, 32, regfile[ARM_PC]);
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-               .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
+               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).valid;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
-               .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
+               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
 
 #if 0
@@ -739,13 +786,13 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        /* current = 1: continue on current pc, otherwise continue at <address> */
        if (!current)
        {
-               buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, ARM_PC).value,
                                0, 32, address);
        }
        else
        {
-               address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, ARM_PC).value,
                                0, 32);
        }
@@ -757,7 +804,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        handle_breakpoints = 1;
        if (handle_breakpoints) {
                breakpoint = breakpoint_find(target,
-                               buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                               buf_get_u32(ARMV4_5_CORE_REG_MODE(
+                                       armv4_5->core_cache,
                                        armv4_5->core_mode, 15).value,
                        0, 32));
                if (breakpoint)
@@ -766,7 +814,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
        /* Setup single step breakpoint */
        stepbreakpoint.address = address;
-       stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
+       stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+                       ? 2 : 4;
        stepbreakpoint.type = BKPT_HARD;
        stepbreakpoint.set = 0;
 
@@ -801,29 +850,84 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
 static int cortex_a8_restore_context(struct target *target)
 {
-       int i;
        uint32_t value;
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+       struct reg_cache *cache = armv7a->armv4_5_common.core_cache;
+       unsigned max = cache->num_regs;
+       struct reg *r;
+       bool flushed, flush_cpsr = false;
 
        LOG_DEBUG(" ");
 
        if (armv7a->pre_restore_context)
                armv7a->pre_restore_context(target);
 
-       for (i = 15; i >= 0; i--)
-       {
-               if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                                       armv4_5->core_mode, i).dirty)
-               {
-                       value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                                               armv4_5->core_mode, i).value,
-                                       0, 32);
+       /* Flush all dirty registers from the cache, one mode at a time so
+        * that we write CPSR as little as possible.  Save CPSR and R0 for
+        * last; they're used to change modes and write other registers.
+        *
+        * REVISIT be smarter:  save eventual mode for last loop, don't
+        * need to write CPSR an extra time.
+        */
+       do {
+               enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+               unsigned i;
+
+               flushed = false;
+
+               /* write dirty non-{R0,CPSR} registers sharing the same mode */
+               for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
+                       struct armv4_5_core_reg *reg;
+
+                       if (!r->dirty || i == ARMV4_5_CPSR)
+                               continue;
+                       reg = r->arch_info;
+
                        /* TODO Check return values */
-                       cortex_a8_dap_write_coreregister_u32(target, value, i);
+
+                       /* Pick a mode and update CPSR; else ignore this
+                        * register if it's for a different mode than what
+                        * we're handling on this pass.
+                        *
+                        * REVISIT don't distinguish SYS and USR modes.
+                        *
+                        * FIXME if we restore from FIQ mode, R8..R12 will
+                        * get wrongly flushed onto FIQ shadows...
+                        */
+                       if (mode == ARMV4_5_MODE_ANY) {
+                               mode = reg->mode;
+                               if (mode != ARMV4_5_MODE_ANY) {
+                                       cortex_a8_dap_write_coreregister_u32(
+                                                       target, mode, 16);
+                                       flush_cpsr = true;
+                               }
+                       } else if (mode != reg->mode)
+                               continue;
+
+                       /* Write this register */
+                       value = buf_get_u32(r->value, 0, 32);
+                       cortex_a8_dap_write_coreregister_u32(target, value,
+                                       (reg->num == 16) ? 17 : reg->num);
+                       r->dirty = false;
+                       flushed = true;
                }
+
+       } while (flushed);
+
+       /* now flush CPSR if needed ... */
+       r = cache->reg_list + ARMV4_5_CPSR;
+       if (flush_cpsr || r->dirty) {
+               value = buf_get_u32(r->value, 0, 32);
+               cortex_a8_dap_write_coreregister_u32(target, value, 16);
+               r->dirty = false;
        }
 
+       /* ... and R0 always (it was dirtied when we saved context) */
+       r = cache->reg_list + 0;
+       value = buf_get_u32(r->value, 0, 32);
+       cortex_a8_dap_write_coreregister_u32(target, value, 0);
+       r->dirty = false;
+
        if (armv7a->post_restore_context)
                armv7a->post_restore_context(target);
 
@@ -860,13 +964,13 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
 
        /* Register other than r0 - r14 uses r0 for access */
        if (num > 14)
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).dirty =
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).valid;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).dirty =
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
 
        return ERROR_OK;
@@ -896,9 +1000,9 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
                if (retval != ERROR_OK)
                {
                        LOG_ERROR("JTAG failure %i", retval);
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, num).dirty =
-                               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, num).valid;
                        return ERROR_JTAG_DEVICE_ERROR;
                }
@@ -914,44 +1018,120 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 #endif
 
 
+static int cortex_a8_write_core_reg(struct target *target, int num,
+               enum armv4_5_mode mode, uint32_t value);
+
 static int cortex_a8_read_core_reg(struct target *target, int num,
                enum armv4_5_mode mode)
 {
        uint32_t value;
        int retval;
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct reg_cache *cache = armv4_5->core_cache;
+       uint32_t cpsr = 0;
+       unsigned cookie = num;
 
-       cortex_a8_dap_read_coreregister_u32(target, &value, num);
+       /* avoid some needless mode changes
+        * FIXME move some of these to shared ARM code...
+        */
+       if (mode != armv4_5->core_mode) {
+               if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+                               && (mode == ARMV4_5_MODE_USR))
+                       mode = ARMV4_5_MODE_ANY;
+               else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+                       mode = ARMV4_5_MODE_ANY;
+
+               if (mode != ARMV4_5_MODE_ANY) {
+                       cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+                                       .value, 0, 32);
+                       cortex_a8_write_core_reg(target, 16,
+                                       ARMV4_5_MODE_ANY, mode);
+               }
+       }
 
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
-               return retval;
+       if (num == 16) {
+               switch (mode) {
+               case ARMV4_5_MODE_USR:
+               case ARMV4_5_MODE_SYS:
+               case ARMV4_5_MODE_ANY:
+                       /* CPSR */
+                       break;
+               default:
+                       /* SPSR */
+                       cookie++;
+                       break;
+               }
        }
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                       mode, num).value, 0, 32, value);
+       cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
+       retval = jtag_execute_queue();
+       if (retval == ERROR_OK) {
+               struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
 
-       return ERROR_OK;
+               r->valid = 1;
+               r->dirty = 0;
+               buf_set_u32(r->value, 0, 32, value);
+       }
+
+       if (cpsr)
+               cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+       return retval;
 }
 
-int cortex_a8_write_core_reg(struct target *target, int num,
+static int cortex_a8_write_core_reg(struct target *target, int num,
                enum armv4_5_mode mode, uint32_t value)
 {
        int retval;
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct reg_cache *cache = armv4_5->core_cache;
+       uint32_t cpsr = 0;
+       unsigned cookie = num;
 
-       cortex_a8_dap_write_coreregister_u32(target, value, num);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
-               return retval;
+       /* avoid some needless mode changes
+        * FIXME move some of these to shared ARM code...
+        */
+       if (mode != armv4_5->core_mode) {
+               if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+                               && (mode == ARMV4_5_MODE_USR))
+                       mode = ARMV4_5_MODE_ANY;
+               else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+                       mode = ARMV4_5_MODE_ANY;
+
+               if (mode != ARMV4_5_MODE_ANY) {
+                       cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+                                       .value, 0, 32);
+                       cortex_a8_write_core_reg(target, 16,
+                                       ARMV4_5_MODE_ANY, mode);
+               }
        }
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
 
-       return ERROR_OK;
+       if (num == 16) {
+               switch (mode) {
+               case ARMV4_5_MODE_USR:
+               case ARMV4_5_MODE_SYS:
+               case ARMV4_5_MODE_ANY:
+                       /* CPSR */
+                       break;
+               default:
+                       /* SPSR */
+                       cookie++;
+                       break;
+               }
+       }
+
+       cortex_a8_dap_write_coreregister_u32(target, value, cookie);
+       if ((retval = jtag_execute_queue()) == ERROR_OK) {
+               struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
+
+               buf_set_u32(r->value, 0, 32, value);
+               r->valid = 1;
+               r->dirty = 0;
+       }
+
+       if (cpsr)
+               cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+       return retval;
 }
 
 
@@ -984,7 +1164,7 @@ static int cortex_a8_set_breakpoint(struct target *target,
                if (brp_i >= cortex_a8->brp_num)
                {
                        LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
-                       exit(-1);
+                       return ERROR_FAIL;
                }
                breakpoint->set = brp_i + 1;
                if (breakpoint->length == 2)
@@ -1142,11 +1322,12 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 static int cortex_a8_assert_reset(struct target *target)
 {
+       struct armv7a_common *armv7a = target_to_armv7a(target);
 
        LOG_DEBUG(" ");
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv7a->armv4_5_common.core_cache);
 
        target->state = TARGET_RESET;
 
@@ -1180,19 +1361,14 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-       int retval = ERROR_OK;
-
-       /* sanitize arguments */
-       if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-               return ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_INVALID_ARGUMENTS;
 
        /* cortex_a8 handles unaligned memory access */
 
 // ??? dap_ap_select(swjdp, swjdp_memoryap);
 
-       switch (size)
-       {
+       if (count && buffer) {
+               switch (size) {
                case 4:
                        retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
@@ -1202,9 +1378,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
                case 1:
                        retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
+               }
        }
 
        return retval;
@@ -1215,17 +1389,12 @@ int cortex_a8_write_memory(struct target *target, uint32_t address,
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-       int retval;
-
-       /* sanitize arguments */
-       if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-               return ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_INVALID_ARGUMENTS;
 
 // ??? dap_ap_select(swjdp, swjdp_memoryap);
 
-       switch (size)
-       {
+       if (count && buffer) {
+               switch (size) {
                case 4:
                        retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
@@ -1235,12 +1404,10 @@ int cortex_a8_write_memory(struct target *target, uint32_t address,
                case 1:
                        retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
+               }
        }
 
-       if (target->state == TARGET_HALTED)
+       if (retval == ERROR_OK && target->state == TARGET_HALTED)
        {
                /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
                /* invalidate I-Cache */
@@ -1297,11 +1464,11 @@ static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_
 static int cortex_a8_handle_target_request(void *priv)
 {
        struct target *target = priv;
-       if (!target->type->examined)
-               return ERROR_OK;
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+       if (!target_was_examined(target))
+               return ERROR_OK;
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
 
@@ -1336,7 +1503,7 @@ static int cortex_a8_handle_target_request(void *priv)
  * Cortex-A8 target information and configuration
  */
 
-static int cortex_a8_examine(struct target *target)
+static int cortex_a8_examine_first(struct target *target)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1421,10 +1588,21 @@ static int cortex_a8_examine(struct target *target)
        LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
                        cortex_a8->brp_num , cortex_a8->wrp_num);
 
-       /* Configure core debug access */
-       cortex_a8_init_debug_access(target);
+       target_set_examined(target);
+       return ERROR_OK;
+}
+
+static int cortex_a8_examine(struct target *target)
+{
+       int retval = ERROR_OK;
+
+       /* don't re-probe hardware after each reset */
+       if (!target_was_examined(target))
+               retval = cortex_a8_examine_first(target);
 
-       target->type->examined = 1;
+       /* Configure core debug access */
+       if (retval == ERROR_OK)
+               retval = cortex_a8_init_debug_access(target);
 
        return retval;
 }
@@ -1438,12 +1616,14 @@ static void cortex_a8_build_reg_cache(struct target *target)
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       armv4_5->core_type = ARM_MODE_MON;
+
        (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
        armv4_5->core_cache = (*cache_p);
 }
 
 
-static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
+static int cortex_a8_init_target(struct command_context *cmd_ctx,
                struct target *target)
 {
        cortex_a8_build_reg_cache(target);
@@ -1453,19 +1633,14 @@ static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
 int cortex_a8_init_arch_info(struct target *target,
                struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
 {
-       struct arm *armv4_5;
-       struct armv7a_common *armv7a;
-
-       armv7a = &cortex_a8->armv7a_common;
-       armv4_5 = &armv7a->armv4_5_common;
+       struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+       struct arm *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
        /* Setup struct cortex_a8_common */
        cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
        armv4_5->arch_info = armv7a;
 
-       armv4_5_init_arch_info(target, armv4_5);
-
        /* prepare JTAG information for the new target */
        cortex_a8->jtag_info.tap = tap;
        cortex_a8->jtag_info.scann_size = 4;
@@ -1505,12 +1680,10 @@ LOG_DEBUG(" ");
 
        armv4_5->read_core_reg = cortex_a8_read_core_reg;
        armv4_5->write_core_reg = cortex_a8_write_core_reg;
-//     armv4_5->full_context = arm7_9_full_context;
 
-//     armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
-//     armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
-//     armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
-//     armv4_5->write_core_reg = armv4_5_write_core_reg;
+       /* REVISIT v7a setup should be in a v7a-specific routine */
+       armv4_5_init_arch_info(target, armv4_5);
+       armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
        target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 
@@ -1528,17 +1701,17 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
 
 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
 {
-       struct target *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
        struct armv7a_common *armv7a = target_to_armv7a(target);
 
-       return armv4_5_handle_cache_info_command(cmd_ctx,
+       return armv4_5_handle_cache_info_command(CMD_CTX,
                        &armv7a->armv4_5_mmu.armv4_5_cache);
 }
 
 
 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 {
-       struct target *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
 
        cortex_a8_init_debug_access(target);
 
@@ -1546,9 +1719,9 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 }
 
 
-static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
+static int cortex_a8_register_commands(struct command_context *cmd_ctx)
 {
-       command_t *cortex_a8_cmd;
+       struct command *cortex_a8_cmd;
        int retval = ERROR_OK;
 
        armv4_5_register_commands(cmd_ctx);
@@ -1590,8 +1763,9 @@ struct target_type cortexa8_target = {
        .read_memory = cortex_a8_read_memory,
        .write_memory = cortex_a8_write_memory,
        .bulk_write_memory = cortex_a8_bulk_write_memory,
-       .checksum_memory = arm7_9_checksum_memory,
-       .blank_check_memory = arm7_9_blank_check_memory,
+
+       .checksum_memory = arm_checksum_memory,
+       .blank_check_memory = arm_blank_check_memory,
 
        .run_algorithm = armv4_5_run_algorithm,
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)