#include "config.h"
#endif
+#include "breakpoints.h"
#include "cortex_a8.h"
-#include "armv7a.h"
-#include "armv4_5.h"
-
+#include "register.h"
#include "target_request.h"
#include "target_type.h"
-static int cortex_a8_poll(target_t *target);
-static int cortex_a8_debug_entry(target_t *target);
-static int cortex_a8_restore_context(target_t *target);
-static int cortex_a8_set_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint, uint8_t matchmode);
-static int cortex_a8_unset_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint);
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_poll(struct target *target);
+static int cortex_a8_debug_entry(struct target *target);
+static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_set_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_unset_breakpoint(struct target *target,
+ struct breakpoint *breakpoint);
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum);
-static int cortex_a8_dap_write_coreregister_u32(target_t *target,
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
/*
* FIXME do topology discovery using the ROM; don't
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
*/
-static int cortex_a8_init_debug_access(target_t *target)
+static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
return retval;
}
-int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
{
uint32_t dscr;
int retval;
Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
-static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
uint32_t * regfile)
{
int retval = ERROR_OK;
return retval;
}
-static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
+static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
return retval;
}
-static int cortex_a8_write_cp(target_t *target, uint32_t value,
+static int cortex_a8_write_cp(struct target *target, uint32_t value,
uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
return retval;
}
-static int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
}
-static int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
{
return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
}
-static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum!=15)
{
return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
}
-static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum!=15)
{
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
int retval = ERROR_OK;
return retval;
}
-static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
}
/* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
+static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
* Cortex-A8 Run control
*/
-static int cortex_a8_poll(target_t *target)
+static int cortex_a8_poll(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
enum target_state prev_target_state = target->state;
return retval;
}
-static int cortex_a8_halt(target_t *target)
+static int cortex_a8_halt(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
return retval;
}
-static int cortex_a8_resume(struct target_s *target, int current,
+static int cortex_a8_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
-// breakpoint_t *breakpoint = NULL;
+// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
return ERROR_OK;
}
-static int cortex_a8_debug_entry(target_t *target)
+static int cortex_a8_debug_entry(struct target *target)
{
int i;
uint32_t regfile[16], pc, cpsr, dscr;
int retval = ERROR_OK;
- working_area_t *regfile_working_area = NULL;
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct working_area *regfile_working_area = NULL;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
}
-static void cortex_a8_post_debug_entry(target_t *target)
+static void cortex_a8_post_debug_entry(struct target *target)
{
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
// cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
}
-static int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+static int cortex_a8_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
- breakpoint_t *breakpoint = NULL;
- breakpoint_t stepbreakpoint;
+ struct breakpoint *breakpoint = NULL;
+ struct breakpoint stepbreakpoint;
int timeout = 100;
return ERROR_OK;
}
-static int cortex_a8_restore_context(target_t *target)
+static int cortex_a8_restore_context(struct target *target)
{
int i;
uint32_t value;
/*
* Cortex-A8 Core register functions
*/
-static int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_load_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
return ERROR_OK;
}
-static int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_store_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t value)
{
int retval;
#endif
-static int cortex_a8_read_core_reg(struct target_s *target, int num,
+static int cortex_a8_read_core_reg(struct target *target, int num,
enum armv4_5_mode mode)
{
uint32_t value;
return ERROR_OK;
}
-int cortex_a8_write_core_reg(struct target_s *target, int num,
+int cortex_a8_write_core_reg(struct target *target, int num,
enum armv4_5_mode mode, uint32_t value)
{
int retval;
*/
/* Setup hardware Breakpoint Register Pair */
-static int cortex_a8_set_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint, uint8_t matchmode)
+static int cortex_a8_set_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode)
{
int retval;
int brp_i=0;
uint32_t control;
uint8_t byte_addr_select = 0x0F;
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
+ struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
if (breakpoint->set)
{
if (brp_i >= cortex_a8->brp_num)
{
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
- exit(-1);
+ return ERROR_FAIL;
}
breakpoint->set = brp_i + 1;
if (breakpoint->length == 2)
return ERROR_OK;
}
-static int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
+ struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
if (!breakpoint->set)
{
return ERROR_OK;
}
-int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
{
return ERROR_OK;
}
-static int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
#if 0
/* It is perfectly possible to remove brakpoints while the taget is running */
* Cortex-A8 Reset fuctions
*/
-static int cortex_a8_assert_reset(target_t *target)
+static int cortex_a8_assert_reset(struct target *target)
{
LOG_DEBUG(" ");
return ERROR_OK;
}
-static int cortex_a8_deassert_reset(target_t *target)
+static int cortex_a8_deassert_reset(struct target *target)
{
LOG_DEBUG(" ");
* ap number for every access.
*/
-static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
+static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
- int retval = ERROR_OK;
-
- /* sanitize arguments */
- if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
- return ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_INVALID_ARGUMENTS;
/* cortex_a8 handles unaligned memory access */
// ??? dap_ap_select(swjdp, swjdp_memoryap);
- switch (size)
- {
+ if (count && buffer) {
+ switch (size) {
case 4:
retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 1:
retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
+ }
}
return retval;
}
-int cortex_a8_write_memory(struct target_s *target, uint32_t address,
+int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
- int retval;
-
- /* sanitize arguments */
- if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
- return ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_INVALID_ARGUMENTS;
// ??? dap_ap_select(swjdp, swjdp_memoryap);
- switch (size)
- {
+ if (count && buffer) {
+ switch (size) {
case 4:
retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 1:
retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
+ }
}
- if (target->state == TARGET_HALTED)
+ if (retval == ERROR_OK && target->state == TARGET_HALTED)
{
/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
/* invalidate I-Cache */
return retval;
}
-static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
{
return cortex_a8_write_memory(target, address, 4, count, buffer);
static int cortex_a8_handle_target_request(void *priv)
{
- target_t *target = priv;
- if (!target->type->examined)
- return ERROR_OK;
+ struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ if (!target_was_examined(target))
+ return ERROR_OK;
if (!target->dbg_msg_enabled)
return ERROR_OK;
* Cortex-A8 target information and configuration
*/
-static int cortex_a8_examine(struct target_s *target)
+static int cortex_a8_examine(struct target *target)
{
- struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
int i;
cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
cortex_a8->brp_num_available = cortex_a8->brp_num;
- cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(cortex_a8_brp_t));
+ cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
// cortex_a8->brb_enabled = ????;
for (i = 0; i < cortex_a8->brp_num; i++)
{
/* Setup Watchpoint Register Pairs */
cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
cortex_a8->wrp_num_available = cortex_a8->wrp_num;
- cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(cortex_a8_wrp_t));
+ cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
for (i = 0; i < cortex_a8->wrp_num; i++)
{
cortex_a8->wrp_list[i].used = 0;
/* Configure core debug access */
cortex_a8_init_debug_access(target);
- target->type->examined = 1;
+ target_set_examined(target);
return retval;
}
* Cortex-A8 target creation and initialization
*/
-static void cortex_a8_build_reg_cache(target_t *target)
+static void cortex_a8_build_reg_cache(struct target *target)
{
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
-static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+static int cortex_a8_init_target(struct command_context *cmd_ctx,
+ struct target *target)
{
cortex_a8_build_reg_cache(target);
return ERROR_OK;
}
-int cortex_a8_init_arch_info(target_t *target,
- cortex_a8_common_t *cortex_a8, struct jtag_tap *tap)
+int cortex_a8_init_arch_info(struct target *target,
+ struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
- armv4_5_common_t *armv4_5;
- struct armv7a_common *armv7a;
-
- armv7a = &cortex_a8->armv7a_common;
- armv4_5 = &armv7a->armv4_5_common;
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
- /* Setup cortex_a8_common_t */
+ /* REVISIT v7a setup should be in a v7a-specific routine */
+ armv4_5_init_arch_info(target, armv4_5);
+ armv7a->common_magic = ARMV7_COMMON_MAGIC;
+
+ /* Setup struct cortex_a8_common */
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
armv4_5->arch_info = armv7a;
- armv4_5_init_arch_info(target, armv4_5);
-
/* prepare JTAG information for the new target */
cortex_a8->jtag_info.tap = tap;
cortex_a8->jtag_info.scann_size = 4;
return ERROR_OK;
}
-static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
+static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
{
- cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t));
+ struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
cortex_a8_init_arch_info(target, cortex_a8, target->tap);
COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
return armv4_5_handle_cache_info_command(cmd_ctx,
COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
cortex_a8_init_debug_access(target);
}
-static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
+static int cortex_a8_register_commands(struct command_context *cmd_ctx)
{
- command_t *cortex_a8_cmd;
+ struct command *cortex_a8_cmd;
int retval = ERROR_OK;
armv4_5_register_commands(cmd_ctx);
return retval;
}
-target_type_t cortexa8_target = {
+struct target_type cortexa8_target = {
.name = "cortex_a8",
.poll = cortex_a8_poll,
.read_memory = cortex_a8_read_memory,
.write_memory = cortex_a8_write_memory,
.bulk_write_memory = cortex_a8_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
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