Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> cortex...

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index dcf246fa52819c1a42d4496e742071553a0a94bd..829bf3dca32f45f980281007c8ffd687847fe334 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -259,14 +259,13 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
 {
        int retval = ERROR_OK;
        uint8_t reg = regnum&0xFF;
+       uint32_t dscr;
 
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
-       swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
        if (reg > 16)
                return retval;
 
@@ -286,10 +285,16 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
 
-       /* Read DCCTX */
+       /* Read DTRRTX */
+       do
+       {
+               retval = mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       }
+       while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+
        retval = mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
-//     retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
 
        return retval;
 }
@@ -408,6 +413,8 @@ int cortex_a8_poll(target_t *target)
 int cortex_a8_halt(target_t *target)
 {
        int retval = ERROR_OK;
+       uint32_t dscr;
+
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -416,13 +423,25 @@ int cortex_a8_halt(target_t *target)
        uint8_t saved_apsel = dap_ap_get_select(swjdp);
        dap_ap_select(swjdp, swjdp_debugap);
 
-       /* Perhaps we should do a read-modify-write here */
+       /*
+        * Tell the core to be halted by writing DRCR with 0x1
+        * and then wait for the core to be halted.
+        */
        retval = mem_ap_write_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
 
+       if (retval != ERROR_OK)
+               goto out;
+
+       do {
+               mem_ap_read_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       } while ((dscr & (1 << 0)) == 0);
+
        target->debug_reason = DBG_REASON_DBGRQ;
-       dap_ap_select(swjdp, saved_apsel);
 
+out:
+       dap_ap_select(swjdp, saved_apsel);
        return retval;
 }
 
@@ -436,7 +455,7 @@ int cortex_a8_resume(struct target_s *target, int current,
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 //     breakpoint_t *breakpoint = NULL;
-       uint32_t resume_pc;
+       uint32_t resume_pc, dscr;
 
        uint8_t saved_apsel = dap_ap_get_select(swjdp);
        dap_ap_select(swjdp, swjdp_debugap);
@@ -510,10 +529,14 @@ int cortex_a8_resume(struct target_s *target, int current,
        }
 
 #endif
-       /* Restart core */
-       /* Perhaps we should do a read-modify-write here */
+       /* Restart core and wait for it to be started */
        mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
 
+       do {
+               mem_ap_read_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       } while ((dscr & (1 << 1)) == 0);
+
        target->debug_reason = DBG_REASON_NOTHALTED;
        target->state = TARGET_RUNNING;
 
@@ -541,7 +564,7 @@ int cortex_a8_resume(struct target_s *target, int current,
 int cortex_a8_debug_entry(target_t *target)
 {
        int i;
-       uint32_t regfile[16], pc, cpsr;
+       uint32_t regfile[16], pc, cpsr, dscr;
        int retval = ERROR_OK;
        working_area_t *regfile_working_area = NULL;
 
@@ -556,6 +579,14 @@ int cortex_a8_debug_entry(target_t *target)
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+       /* Enable the ITR execution once we are in debug mode */
+       mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       dscr |= (1 << 13);
+       retval = mem_ap_write_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+
+
        /* Examine debug reason */
        switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
        {
@@ -576,7 +607,6 @@ int cortex_a8_debug_entry(target_t *target)
        }
 
        /* Examine target state and mode */
-       dap_ap_select(swjdp, swjdp_memoryap);
        if (cortex_a8->fast_reg_read)
                target_alloc_working_area(target, 64, &regfile_working_area);
 
@@ -589,6 +619,7 @@ int cortex_a8_debug_entry(target_t *target)
        }
        else
        {
+               dap_ap_select(swjdp, swjdp_memoryap);
                cortex_a8_read_regs_through_mem(target,
                                regfile_working_area->address, regfile);
                dap_ap_select(swjdp, swjdp_memoryap);