int cortex_a8_halt(target_t *target)
{
int retval = ERROR_OK;
+ uint32_t dscr;
+
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
- /* Perhaps we should do a read-modify-write here */
+ /*
+ * Tell the core to be halted by writing DRCR with 0x1
+ * and then wait for the core to be halted.
+ */
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
+ if (retval != ERROR_OK)
+ goto out;
+
+ do {
+ mem_ap_read_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ } while ((dscr & (1 << 0)) == 0);
+
target->debug_reason = DBG_REASON_DBGRQ;
- dap_ap_select(swjdp, saved_apsel);
+out:
+ dap_ap_select(swjdp, saved_apsel);
return retval;
}
swjdp_common_t *swjdp = &armv7a->swjdp_info;
// breakpoint_t *breakpoint = NULL;
- uint32_t resume_pc;
+ uint32_t resume_pc, dscr;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
}
#endif
- /* Restart core */
- /* Perhaps we should do a read-modify-write here */
+ /* Restart core and wait for it to be started */
mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
+ do {
+ mem_ap_read_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ } while ((dscr & (1 << 1)) == 0);
+
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
int cortex_a8_debug_entry(target_t *target)
{
int i;
- uint32_t regfile[16], pc, cpsr;
+ uint32_t regfile[16], pc, cpsr, dscr;
int retval = ERROR_OK;
working_area_t *regfile_working_area = NULL;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
+ /* Enable the ITR execution once we are in debug mode */
+ mem_ap_read_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ dscr |= (1 << 13);
+ retval = mem_ap_write_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+
+
/* Examine debug reason */
switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
{
}
/* Examine target state and mode */
- dap_ap_select(swjdp, swjdp_memoryap);
if (cortex_a8->fast_reg_read)
target_alloc_working_area(target, 64, ®file_working_area);
}
else
{
+ dap_ap_select(swjdp, swjdp_memoryap);
cortex_a8_read_regs_through_mem(target,
regfile_working_area->address, regfile);
dap_ap_select(swjdp, swjdp_memoryap);