It is not possible to invalidate I-Cache on memory writes while the target is running

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 821d7194eb63d1613ee02398e80d78c85fc58081..846d90c343360367317ed2267c8e1ec42bd4c3f3 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -236,11 +236,25 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
        uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
        int retval;
+       uint32_t dscr;
+
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
+       LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
+
+       /* Check that DCCRX is not full */
+       retval = mem_ap_read_atomic_u32(swjdp,
+                               armv7a->debug_base + CPUDBG_DSCR, &dscr);
+       if (dscr & (1 << DSCR_DTR_RX_FULL))
+       {
+               LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+               /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+       }
+       
        retval = mem_ap_write_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DTRRX, value);
        /* Move DTRRX to r0 */
@@ -311,12 +325,25 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
 {
        int retval = ERROR_OK;
        uint8_t Rd = regnum&0xFF;
+       uint32_t dscr;
 
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
        
+       LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
+
+       /* Check that DCCRX is not full */
+       retval = mem_ap_read_atomic_u32(swjdp,
+                               armv7a->debug_base + CPUDBG_DSCR, &dscr);
+       if (dscr & (1 << DSCR_DTR_RX_FULL))
+       {
+               LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+               /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+       }
+       
        if (Rd > 16)
                return retval;
 
@@ -1305,6 +1332,8 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                        exit(-1);
        }
 
+       if (target->state == TARGET_HALTED)
+       {
                /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
                /* invalidate I-Cache */
                if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
@@ -1322,6 +1351,7 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                        for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
                                armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
                }
+       }
 
        return retval;
 }