Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 84ace67db20cd405658d856027bfc481cd23be8f..9585b35c2a658cb0de9980ce5b99b6ac854234c2 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -161,7 +161,15 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
        LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
+       do
+       {
+               retvalue = mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       }
+       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+
        mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+
        do
        {
                retvalue = mem_ap_read_atomic_u32(swjdp,
@@ -251,14 +259,13 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
 {
        int retval = ERROR_OK;
        uint8_t reg = regnum&0xFF;
+       uint32_t dscr;
 
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
-       swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
        if (reg > 16)
                return retval;
 
@@ -278,10 +285,16 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
 
-       /* Read DCCTX */
+       /* Read DTRRTX */
+       do
+       {
+               retval = mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       }
+       while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+
        retval = mem_ap_read_atomic_u32(swjdp,
                        OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
-//     retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
 
        return retval;
 }
@@ -533,7 +546,7 @@ int cortex_a8_resume(struct target_s *target, int current,
 int cortex_a8_debug_entry(target_t *target)
 {
        int i;
-       uint32_t regfile[16], pc, cpsr;
+       uint32_t regfile[16], pc, cpsr, dscr;
        int retval = ERROR_OK;
        working_area_t *regfile_working_area = NULL;
 
@@ -548,6 +561,14 @@ int cortex_a8_debug_entry(target_t *target)
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+       /* Enable the ITR execution once we are in debug mode */
+       mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       dscr |= (1 << 13);
+       retval = mem_ap_write_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+
+
        /* Examine debug reason */
        switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
        {