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target: create/use register_cache_invalidate()
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index f8ff3920e3eff553ec28ba52960bf9ce423e9355..d02fee9e17affa30f904c726d8a4913e9b59d9dc 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -242,16 +242,18 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 
        if (reg < 15)
        {
-               /* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+               /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
        }
        else if (reg == 15)
        {
+               /* "MOV r0, r15"; then move r0 to DCCTX */
                cortex_a8_exec_opcode(target, 0xE1A0000F);
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
        else if (reg == 16)
        {
+               /* "MRS r0, CPSR"; then move r0 to DCCTX */
                cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
@@ -480,7 +482,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        resume_pc = buf_get_u32(
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
                        0, 32);
        if (!current)
@@ -489,24 +491,29 @@ static int cortex_a8_resume(struct target *target, int current,
        /* Make sure that the Armv7 gdb thumb fixups does not
         * kill the return address
         */
-       if (armv7a->core_state == ARMV7A_STATE_ARM)
+       switch (armv4_5->core_state)
        {
+       case ARMV4_5_STATE_ARM:
                resume_pc &= 0xFFFFFFFC;
-       }
-       /* When the return address is loaded into PC
-        * bit 0 must be 1 to stay in Thumb state
-        */
-       if (armv7a->core_state == ARMV7A_STATE_THUMB)
-       {
+               break;
+       case ARMV4_5_STATE_THUMB:
+       case ARM_STATE_THUMB_EE:
+               /* When the return address is loaded into PC
+                * bit 0 must be 1 to stay in Thumb state
+                */
                resume_pc |= 0x1;
+               break;
+       case ARMV4_5_STATE_JAZELLE:
+               LOG_ERROR("How do I resume into Jazelle state??");
+               return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
                        0, 32, resume_pc);
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        armv4_5->core_mode, 15).dirty = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        armv4_5->core_mode, 15).valid = 1;
 
        cortex_a8_restore_context(target);
@@ -538,7 +545,7 @@ static int cortex_a8_resume(struct target *target, int current,
        target->state = TARGET_RUNNING;
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv4_5->core_cache);
 
        if (!debug_execution)
        {
@@ -568,6 +575,7 @@ static int cortex_a8_debug_entry(struct target *target)
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
+       struct reg *reg;
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
@@ -604,6 +612,9 @@ static int cortex_a8_debug_entry(struct target *target)
        /* First load register acessible through core debug port*/
        if (!regfile_working_area)
        {
+               /* FIXME we don't actually need all these registers;
+                * reading them slows us down.  Just R0, PC, CPSR...
+                */
                for (i = 0; i <= 15; i++)
                        cortex_a8_dap_read_coreregister_u32(target,
                                        &regfile[i], i);
@@ -617,32 +628,55 @@ static int cortex_a8_debug_entry(struct target *target)
                target_free_working_area(target, regfile_working_area);
        }
 
+       /* read Current PSR */
        cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
        pc = regfile[15];
        dap_ap_select(swjdp, swjdp_debugap);
        LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
        armv4_5->core_mode = cpsr & 0x1F;
-       armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
+
+       i = (cpsr >> 5) & 1;    /* T */
+       i |= (cpsr >> 23) & 1;  /* J << 1 */
+       switch (i) {
+       case 0: /* J = 0, T = 0 */
+               armv4_5->core_state = ARMV4_5_STATE_ARM;
+               break;
+       case 1: /* J = 0, T = 1 */
+               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               break;
+       case 2: /* J = 1, T = 0 */
+               LOG_WARNING("Jazelle state -- not handled");
+               armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+               break;
+       case 3: /* J = 1, T = 1 */
+               /* ThumbEE is very much like Thumb, but some of the
+                * instructions are different.  Single stepping and
+                * breakpoints need updating...
+                */
+               LOG_WARNING("ThumbEE -- incomplete support");
+               armv4_5->core_state = ARM_STATE_THUMB_EE;
+               break;
+       }
+
+       /* update cache */
+       reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
+       buf_set_u32(reg->value, 0, 32, cpsr);
+       reg->valid = 1;
+       reg->dirty = 0;
 
        for (i = 0; i <= ARM_PC; i++)
        {
-               buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                                       armv4_5->core_mode, i).value,
-                               0, 32, regfile[i]);
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, i).valid = 1;
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, i).dirty = 0;
-       }
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 16).value,
-                       0, 32, cpsr);
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
+               reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+                                       armv4_5->core_mode, i);
+
+               buf_set_u32(reg->value, 0, 32, regfile[i]);
+               reg->valid = 1;
+               reg->dirty = 0;
+       }
 
        /* Fixup PC Resume Address */
-       if (armv7a->core_state == ARMV7A_STATE_THUMB)
+       if (cpsr & (1 << 5))
        {
                // T bit set for Thumb or ThumbEE state
                regfile[ARM_PC] -= 4;
@@ -652,15 +686,15 @@ static int cortex_a8_debug_entry(struct target *target)
                // ARM state
                regfile[ARM_PC] -= 8;
        }
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, ARM_PC).value,
                        0, 32, regfile[ARM_PC]);
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-               .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
+               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).valid;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
-               .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
+               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
 
 #if 0
@@ -738,13 +772,13 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        /* current = 1: continue on current pc, otherwise continue at <address> */
        if (!current)
        {
-               buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, ARM_PC).value,
                                0, 32, address);
        }
        else
        {
-               address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, ARM_PC).value,
                                0, 32);
        }
@@ -756,7 +790,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        handle_breakpoints = 1;
        if (handle_breakpoints) {
                breakpoint = breakpoint_find(target,
-                               buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                               buf_get_u32(ARMV4_5_CORE_REG_MODE(
+                                       armv4_5->core_cache,
                                        armv4_5->core_mode, 15).value,
                        0, 32));
                if (breakpoint)
@@ -765,7 +800,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
        /* Setup single step breakpoint */
        stepbreakpoint.address = address;
-       stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
+       stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+                       ? 2 : 4;
        stepbreakpoint.type = BKPT_HARD;
        stepbreakpoint.set = 0;
 
@@ -812,10 +848,11 @@ static int cortex_a8_restore_context(struct target *target)
 
        for (i = 15; i >= 0; i--)
        {
-               if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, i).dirty)
                {
-                       value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
+                                               armv4_5->core_cache,
                                                armv4_5->core_mode, i).value,
                                        0, 32);
                        /* TODO Check return values */
@@ -859,13 +896,13 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
 
        /* Register other than r0 - r14 uses r0 for access */
        if (num > 14)
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).dirty =
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).valid;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).dirty =
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
 
        return ERROR_OK;
@@ -895,9 +932,9 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
                if (retval != ERROR_OK)
                {
                        LOG_ERROR("JTAG failure %i", retval);
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, num).dirty =
-                               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, num).valid;
                        return ERROR_JTAG_DEVICE_ERROR;
                }
@@ -920,6 +957,8 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
        int retval;
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       /* FIXME cortex may not be in "mode" ... */
+
        cortex_a8_dap_read_coreregister_u32(target, &value, num);
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -927,28 +966,30 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
                return retval;
        }
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        mode, num).value, 0, 32, value);
 
        return ERROR_OK;
 }
 
-int cortex_a8_write_core_reg(struct target *target, int num,
+static int cortex_a8_write_core_reg(struct target *target, int num,
                enum armv4_5_mode mode, uint32_t value)
 {
        int retval;
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       /* FIXME cortex may not be in "mode" ... */
+
        cortex_a8_dap_write_coreregister_u32(target, value, num);
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                return retval;
        }
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
 
        return ERROR_OK;
 }
@@ -1141,11 +1182,12 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 static int cortex_a8_assert_reset(struct target *target)
 {
+       struct armv7a_common *armv7a = target_to_armv7a(target);
 
        LOG_DEBUG(" ");
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv7a->armv4_5_common.core_cache);
 
        target->state = TARGET_RESET;
 
@@ -1321,7 +1363,7 @@ static int cortex_a8_handle_target_request(void *priv)
  * Cortex-A8 target information and configuration
  */
 
-static int cortex_a8_examine(struct target *target)
+static int cortex_a8_examine_first(struct target *target)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1406,10 +1448,21 @@ static int cortex_a8_examine(struct target *target)
        LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
                        cortex_a8->brp_num , cortex_a8->wrp_num);
 
-       /* Configure core debug access */
-       cortex_a8_init_debug_access(target);
-
        target_set_examined(target);
+       return ERROR_OK;
+}
+
+static int cortex_a8_examine(struct target *target)
+{
+       int retval = ERROR_OK;
+
+       /* don't re-probe hardware after each reset */
+       if (!target_was_examined(target))
+               retval = cortex_a8_examine_first(target);
+
+       /* Configure core debug access */
+       if (retval == ERROR_OK)
+               retval = cortex_a8_init_debug_access(target);
 
        return retval;
 }
@@ -1444,10 +1497,6 @@ int cortex_a8_init_arch_info(struct target *target,
        struct arm *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
-       /* REVISIT v7a setup should be in a v7a-specific routine */
-       armv4_5_init_arch_info(target, armv4_5);
-       armv7a->common_magic = ARMV7_COMMON_MAGIC;
-
        /* Setup struct cortex_a8_common */
        cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
        armv4_5->arch_info = armv7a;
@@ -1491,12 +1540,10 @@ LOG_DEBUG(" ");
 
        armv4_5->read_core_reg = cortex_a8_read_core_reg;
        armv4_5->write_core_reg = cortex_a8_write_core_reg;
-//     armv4_5->full_context = arm7_9_full_context;
 
-//     armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
-//     armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
-//     armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
-//     armv4_5->write_core_reg = armv4_5_write_core_reg;
+       /* REVISIT v7a setup should be in a v7a-specific routine */
+       armv4_5_init_arch_info(target, armv4_5);
+       armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
        target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 
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