target: create/use register_cache_invalidate()

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index fc788446f194874fc1288c90a4bb9ffb28117d69..d02fee9e17affa30f904c726d8a4913e9b59d9dc 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -491,16 +491,21 @@ static int cortex_a8_resume(struct target *target, int current,
        /* Make sure that the Armv7 gdb thumb fixups does not
         * kill the return address
         */
-       if (armv7a->core_state == ARMV7A_STATE_ARM)
+       switch (armv4_5->core_state)
        {
+       case ARMV4_5_STATE_ARM:
                resume_pc &= 0xFFFFFFFC;
-       }
-       /* When the return address is loaded into PC
-        * bit 0 must be 1 to stay in Thumb state
-        */
-       if (armv7a->core_state == ARMV7A_STATE_THUMB)
-       {
+               break;
+       case ARMV4_5_STATE_THUMB:
+       case ARM_STATE_THUMB_EE:
+               /* When the return address is loaded into PC
+                * bit 0 must be 1 to stay in Thumb state
+                */
                resume_pc |= 0x1;
+               break;
+       case ARMV4_5_STATE_JAZELLE:
+               LOG_ERROR("How do I resume into Jazelle state??");
+               return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
        buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
@@ -540,7 +545,7 @@ static int cortex_a8_resume(struct target *target, int current,
        target->state = TARGET_RUNNING;
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv4_5->core_cache);
 
        if (!debug_execution)
        {
@@ -630,9 +635,29 @@ static int cortex_a8_debug_entry(struct target *target)
        LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
        armv4_5->core_mode = cpsr & 0x1F;
-       armv7a->core_state = (cpsr & 0x20)
-                       ? ARMV7A_STATE_THUMB
-                       : ARMV7A_STATE_ARM;
+
+       i = (cpsr >> 5) & 1;    /* T */
+       i |= (cpsr >> 23) & 1;  /* J << 1 */
+       switch (i) {
+       case 0: /* J = 0, T = 0 */
+               armv4_5->core_state = ARMV4_5_STATE_ARM;
+               break;
+       case 1: /* J = 0, T = 1 */
+               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               break;
+       case 2: /* J = 1, T = 0 */
+               LOG_WARNING("Jazelle state -- not handled");
+               armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+               break;
+       case 3: /* J = 1, T = 1 */
+               /* ThumbEE is very much like Thumb, but some of the
+                * instructions are different.  Single stepping and
+                * breakpoints need updating...
+                */
+               LOG_WARNING("ThumbEE -- incomplete support");
+               armv4_5->core_state = ARM_STATE_THUMB_EE;
+               break;
+       }
 
        /* update cache */
        reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
@@ -651,7 +676,7 @@ static int cortex_a8_debug_entry(struct target *target)
        }
 
        /* Fixup PC Resume Address */
-       if (armv7a->core_state == ARMV7A_STATE_THUMB)
+       if (cpsr & (1 << 5))
        {
                // T bit set for Thumb or ThumbEE state
                regfile[ARM_PC] -= 4;
@@ -775,7 +800,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
        /* Setup single step breakpoint */
        stepbreakpoint.address = address;
-       stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
+       stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+                       ? 2 : 4;
        stepbreakpoint.type = BKPT_HARD;
        stepbreakpoint.set = 0;
 
@@ -1156,11 +1182,12 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 static int cortex_a8_assert_reset(struct target *target)
 {
+       struct armv7a_common *armv7a = target_to_armv7a(target);
 
        LOG_DEBUG(" ");
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv7a->armv4_5_common.core_cache);
 
        target->state = TARGET_RESET;
 
@@ -1336,7 +1363,7 @@ static int cortex_a8_handle_target_request(void *priv)
  * Cortex-A8 target information and configuration
  */
 
-static int cortex_a8_examine(struct target *target)
+static int cortex_a8_examine_first(struct target *target)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1421,10 +1448,21 @@ static int cortex_a8_examine(struct target *target)
        LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
                        cortex_a8->brp_num , cortex_a8->wrp_num);
 
-       /* Configure core debug access */
-       cortex_a8_init_debug_access(target);
-
        target_set_examined(target);
+       return ERROR_OK;
+}
+
+static int cortex_a8_examine(struct target *target)
+{
+       int retval = ERROR_OK;
+
+       /* don't re-probe hardware after each reset */
+       if (!target_was_examined(target))
+               retval = cortex_a8_examine_first(target);
+
+       /* Configure core debug access */
+       if (retval == ERROR_OK)
+               retval = cortex_a8_init_debug_access(target);
 
        return retval;
 }