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Cortex-A8: xPSR handling updates
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 82d0b281907ec548a497217a8e4cdb7a1c331fc5..fc788446f194874fc1288c90a4bb9ffb28117d69 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -33,23 +33,22 @@
 #include "config.h"
 #endif
 
+#include "breakpoints.h"
 #include "cortex_a8.h"
-#include "armv7a.h"
-#include "armv4_5.h"
-
+#include "register.h"
 #include "target_request.h"
 #include "target_type.h"
 
-static int cortex_a8_poll(target_t *target);
-static int cortex_a8_debug_entry(target_t *target);
-static int cortex_a8_restore_context(target_t *target);
-static int cortex_a8_set_breakpoint(struct target_s *target,
+static int cortex_a8_poll(struct target *target);
+static int cortex_a8_debug_entry(struct target *target);
+static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_set_breakpoint(struct target *target,
                struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_unset_breakpoint(struct target_s *target,
+static int cortex_a8_unset_breakpoint(struct target *target,
                struct breakpoint *breakpoint);
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
                uint32_t *value, int regnum);
-static int cortex_a8_dap_write_coreregister_u32(target_t *target,
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
                uint32_t value, int regnum);
 /*
  * FIXME do topology discovery using the ROM; don't
@@ -62,7 +61,7 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target,
 /*
  * Cortex-A8 Basic debug access, very low level assumes state is saved
  */
-static int cortex_a8_init_debug_access(target_t *target)
+static int cortex_a8_init_debug_access(struct target *target)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
@@ -90,7 +89,7 @@ static int cortex_a8_init_debug_access(target_t *target)
        return retval;
 }
 
-int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
 {
        uint32_t dscr;
        int retval;
@@ -131,7 +130,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 Read core register with very few exec_opcode, fast but needs work_area.
 This can cause problems with MMU active.
 **************************************************************************/
-static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
                uint32_t * regfile)
 {
        int retval = ERROR_OK;
@@ -148,7 +147,7 @@ static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
        return retval;
 }
 
-static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
+static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
                uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
        int retval;
@@ -166,7 +165,7 @@ static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
        return retval;
 }
 
-static int cortex_a8_write_cp(target_t *target, uint32_t value,
+static int cortex_a8_write_cp(struct target *target, uint32_t value,
        uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
        int retval;
@@ -195,19 +194,19 @@ static int cortex_a8_write_cp(target_t *target, uint32_t value,
        return retval;
 }
 
-static int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
                uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
        return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
 }
 
-static int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
                uint32_t CRn, uint32_t CRm, uint32_t value)
 {
        return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
 }
 
-static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
        if (cpnum!=15)
        {
@@ -217,7 +216,7 @@ static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2
        return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
 }
 
-static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
        if (cpnum!=15)
        {
@@ -229,7 +228,7 @@ static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2
 
 
 
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
                uint32_t *value, int regnum)
 {
        int retval = ERROR_OK;
@@ -243,16 +242,18 @@ static int cortex_a8_dap_read_coreregister_u32(target_t *target,
 
        if (reg < 15)
        {
-               /* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+               /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
        }
        else if (reg == 15)
        {
+               /* "MOV r0, r15"; then move r0 to DCCTX */
                cortex_a8_exec_opcode(target, 0xE1A0000F);
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
        else if (reg == 16)
        {
+               /* "MRS r0, CPSR"; then move r0 to DCCTX */
                cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
                cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
@@ -271,7 +272,7 @@ static int cortex_a8_dap_read_coreregister_u32(target_t *target,
        return retval;
 }
 
-static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
 {
        int retval = ERROR_OK;
        uint8_t Rd = regnum&0xFF;
@@ -320,7 +321,7 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value
 }
 
 /* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
+static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
 {
        int retval;
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -335,7 +336,7 @@ static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t add
  * Cortex-A8 Run control
  */
 
-static int cortex_a8_poll(target_t *target)
+static int cortex_a8_poll(struct target *target)
 {
        int retval = ERROR_OK;
        uint32_t dscr;
@@ -400,7 +401,7 @@ static int cortex_a8_poll(target_t *target)
        return retval;
 }
 
-static int cortex_a8_halt(target_t *target)
+static int cortex_a8_halt(struct target *target)
 {
        int retval = ERROR_OK;
        uint32_t dscr;
@@ -438,7 +439,7 @@ out:
        return retval;
 }
 
-static int cortex_a8_resume(struct target_s *target, int current,
+static int cortex_a8_resume(struct target *target, int current,
                uint32_t address, int handle_breakpoints, int debug_execution)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -481,7 +482,7 @@ static int cortex_a8_resume(struct target_s *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        resume_pc = buf_get_u32(
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
                        0, 32);
        if (!current)
@@ -502,12 +503,12 @@ static int cortex_a8_resume(struct target_s *target, int current,
                resume_pc |= 0x1;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).value,
                        0, 32, resume_pc);
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        armv4_5->core_mode, 15).dirty = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        armv4_5->core_mode, 15).valid = 1;
 
        cortex_a8_restore_context(target);
@@ -559,7 +560,7 @@ static int cortex_a8_resume(struct target_s *target, int current,
        return ERROR_OK;
 }
 
-static int cortex_a8_debug_entry(target_t *target)
+static int cortex_a8_debug_entry(struct target *target)
 {
        int i;
        uint32_t regfile[16], pc, cpsr, dscr;
@@ -569,6 +570,7 @@ static int cortex_a8_debug_entry(target_t *target)
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
+       struct reg *reg;
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
@@ -605,6 +607,9 @@ static int cortex_a8_debug_entry(target_t *target)
        /* First load register acessible through core debug port*/
        if (!regfile_working_area)
        {
+               /* FIXME we don't actually need all these registers;
+                * reading them slows us down.  Just R0, PC, CPSR...
+                */
                for (i = 0; i <= 15; i++)
                        cortex_a8_dap_read_coreregister_u32(target,
                                        &regfile[i], i);
@@ -618,29 +623,32 @@ static int cortex_a8_debug_entry(target_t *target)
                target_free_working_area(target, regfile_working_area);
        }
 
+       /* read Current PSR */
        cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
        pc = regfile[15];
        dap_ap_select(swjdp, swjdp_debugap);
        LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
        armv4_5->core_mode = cpsr & 0x1F;
-       armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
+       armv7a->core_state = (cpsr & 0x20)
+                       ? ARMV7A_STATE_THUMB
+                       : ARMV7A_STATE_ARM;
+
+       /* update cache */
+       reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
+       buf_set_u32(reg->value, 0, 32, cpsr);
+       reg->valid = 1;
+       reg->dirty = 0;
 
        for (i = 0; i <= ARM_PC; i++)
        {
-               buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                                       armv4_5->core_mode, i).value,
-                               0, 32, regfile[i]);
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, i).valid = 1;
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, i).dirty = 0;
-       }
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 16).value,
-                       0, 32, cpsr);
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
+               reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+                                       armv4_5->core_mode, i);
+
+               buf_set_u32(reg->value, 0, 32, regfile[i]);
+               reg->valid = 1;
+               reg->dirty = 0;
+       }
 
        /* Fixup PC Resume Address */
        if (armv7a->core_state == ARMV7A_STATE_THUMB)
@@ -653,15 +661,15 @@ static int cortex_a8_debug_entry(target_t *target)
                // ARM state
                regfile[ARM_PC] -= 8;
        }
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, ARM_PC).value,
                        0, 32, regfile[ARM_PC]);
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-               .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
+               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).valid;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
-               .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
+               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
 
 #if 0
@@ -688,7 +696,7 @@ static int cortex_a8_debug_entry(target_t *target)
 
 }
 
-static void cortex_a8_post_debug_entry(target_t *target)
+static void cortex_a8_post_debug_entry(struct target *target)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -720,7 +728,7 @@ static void cortex_a8_post_debug_entry(target_t *target)
 
 }
 
-static int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+static int cortex_a8_step(struct target *target, int current, uint32_t address,
                int handle_breakpoints)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -739,13 +747,13 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address
        /* current = 1: continue on current pc, otherwise continue at <address> */
        if (!current)
        {
-               buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, ARM_PC).value,
                                0, 32, address);
        }
        else
        {
-               address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, ARM_PC).value,
                                0, 32);
        }
@@ -757,7 +765,8 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address
        handle_breakpoints = 1;
        if (handle_breakpoints) {
                breakpoint = breakpoint_find(target,
-                               buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                               buf_get_u32(ARMV4_5_CORE_REG_MODE(
+                                       armv4_5->core_cache,
                                        armv4_5->core_mode, 15).value,
                        0, 32));
                if (breakpoint)
@@ -799,7 +808,7 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address
        return ERROR_OK;
 }
 
-static int cortex_a8_restore_context(target_t *target)
+static int cortex_a8_restore_context(struct target *target)
 {
        int i;
        uint32_t value;
@@ -813,10 +822,11 @@ static int cortex_a8_restore_context(target_t *target)
 
        for (i = 15; i >= 0; i--)
        {
-               if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, i).dirty)
                {
-                       value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
+                                               armv4_5->core_cache,
                                                armv4_5->core_mode, i).value,
                                        0, 32);
                        /* TODO Check return values */
@@ -835,7 +845,7 @@ static int cortex_a8_restore_context(target_t *target)
 /*
  * Cortex-A8 Core register functions
  */
-static int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_load_core_reg_u32(struct target *target, int num,
                armv4_5_mode_t mode, uint32_t * value)
 {
        int retval;
@@ -860,19 +870,19 @@ static int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
 
        /* Register other than r0 - r14 uses r0 for access */
        if (num > 14)
-               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).dirty =
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 0).valid;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).dirty =
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
 
        return ERROR_OK;
 }
 
-static int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_store_core_reg_u32(struct target *target, int num,
                armv4_5_mode_t mode, uint32_t value)
 {
        int retval;
@@ -896,9 +906,9 @@ static int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
                if (retval != ERROR_OK)
                {
                        LOG_ERROR("JTAG failure %i", retval);
-                       ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, num).dirty =
-                               ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+                               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        armv4_5->core_mode, num).valid;
                        return ERROR_JTAG_DEVICE_ERROR;
                }
@@ -914,13 +924,15 @@ static int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
 #endif
 
 
-static int cortex_a8_read_core_reg(struct target_s *target, int num,
+static int cortex_a8_read_core_reg(struct target *target, int num,
                enum armv4_5_mode mode)
 {
        uint32_t value;
        int retval;
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       /* FIXME cortex may not be in "mode" ... */
+
        cortex_a8_dap_read_coreregister_u32(target, &value, num);
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -928,28 +940,30 @@ static int cortex_a8_read_core_reg(struct target_s *target, int num,
                return retval;
        }
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-       buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                        mode, num).value, 0, 32, value);
 
        return ERROR_OK;
 }
 
-int cortex_a8_write_core_reg(struct target_s *target, int num,
+static int cortex_a8_write_core_reg(struct target *target, int num,
                enum armv4_5_mode mode, uint32_t value)
 {
        int retval;
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       /* FIXME cortex may not be in "mode" ... */
+
        cortex_a8_dap_write_coreregister_u32(target, value, num);
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                return retval;
        }
 
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
 
        return ERROR_OK;
 }
@@ -960,7 +974,7 @@ int cortex_a8_write_core_reg(struct target_s *target, int num,
  */
 
 /* Setup hardware Breakpoint Register Pair */
-static int cortex_a8_set_breakpoint(struct target_s *target,
+static int cortex_a8_set_breakpoint(struct target *target,
                struct breakpoint *breakpoint, uint8_t matchmode)
 {
        int retval;
@@ -984,7 +998,7 @@ static int cortex_a8_set_breakpoint(struct target_s *target,
                if (brp_i >= cortex_a8->brp_num)
                {
                        LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
-                       exit(-1);
+                       return ERROR_FAIL;
                }
                breakpoint->set = brp_i + 1;
                if (breakpoint->length == 2)
@@ -1035,7 +1049,7 @@ static int cortex_a8_set_breakpoint(struct target_s *target,
        return ERROR_OK;
 }
 
-static int cortex_a8_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        int retval;
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -1093,7 +1107,7 @@ static int cortex_a8_unset_breakpoint(struct target_s *target, struct breakpoint
        return ERROR_OK;
 }
 
-int cortex_a8_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
@@ -1110,7 +1124,7 @@ int cortex_a8_add_breakpoint(struct target_s *target, struct breakpoint *breakpo
        return ERROR_OK;
 }
 
-static int cortex_a8_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
@@ -1140,7 +1154,7 @@ static int cortex_a8_remove_breakpoint(struct target_s *target, struct breakpoin
  * Cortex-A8 Reset fuctions
  */
 
-static int cortex_a8_assert_reset(target_t *target)
+static int cortex_a8_assert_reset(struct target *target)
 {
 
        LOG_DEBUG(" ");
@@ -1153,7 +1167,7 @@ static int cortex_a8_assert_reset(target_t *target)
        return ERROR_OK;
 }
 
-static int cortex_a8_deassert_reset(target_t *target)
+static int cortex_a8_deassert_reset(struct target *target)
 {
 
        LOG_DEBUG(" ");
@@ -1175,24 +1189,19 @@ static int cortex_a8_deassert_reset(target_t *target)
  * ap number for every access.
  */
 
-static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
+static int cortex_a8_read_memory(struct target *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-       int retval = ERROR_OK;
-
-       /* sanitize arguments */
-       if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-               return ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_INVALID_ARGUMENTS;
 
        /* cortex_a8 handles unaligned memory access */
 
 // ??? dap_ap_select(swjdp, swjdp_memoryap);
 
-       switch (size)
-       {
+       if (count && buffer) {
+               switch (size) {
                case 4:
                        retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
@@ -1202,30 +1211,23 @@ static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
                case 1:
                        retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
+               }
        }
 
        return retval;
 }
 
-int cortex_a8_write_memory(struct target_s *target, uint32_t address,
+int cortex_a8_write_memory(struct target *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-       int retval;
-
-       /* sanitize arguments */
-       if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-               return ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_INVALID_ARGUMENTS;
 
 // ??? dap_ap_select(swjdp, swjdp_memoryap);
 
-       switch (size)
-       {
+       if (count && buffer) {
+               switch (size) {
                case 4:
                        retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
@@ -1235,12 +1237,10 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                case 1:
                        retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
+               }
        }
 
-       if (target->state == TARGET_HALTED)
+       if (retval == ERROR_OK && target->state == TARGET_HALTED)
        {
                /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
                /* invalidate I-Cache */
@@ -1264,7 +1264,7 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
        return retval;
 }
 
-static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
                uint32_t count, uint8_t *buffer)
 {
        return cortex_a8_write_memory(target, address, 4, count, buffer);
@@ -1296,12 +1296,12 @@ static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_
 
 static int cortex_a8_handle_target_request(void *priv)
 {
-       target_t *target = priv;
-       if (!target->type->examined)
-               return ERROR_OK;
+       struct target *target = priv;
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+       if (!target_was_examined(target))
+               return ERROR_OK;
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
 
@@ -1336,7 +1336,7 @@ static int cortex_a8_handle_target_request(void *priv)
  * Cortex-A8 target information and configuration
  */
 
-static int cortex_a8_examine(struct target_s *target)
+static int cortex_a8_examine(struct target *target)
 {
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1424,7 +1424,7 @@ static int cortex_a8_examine(struct target_s *target)
        /* Configure core debug access */
        cortex_a8_init_debug_access(target);
 
-       target->type->examined = 1;
+       target_set_examined(target);
 
        return retval;
 }
@@ -1433,39 +1433,36 @@ static int cortex_a8_examine(struct target_s *target)
  *     Cortex-A8 target creation and initialization
  */
 
-static void cortex_a8_build_reg_cache(target_t *target)
+static void cortex_a8_build_reg_cache(struct target *target)
 {
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       armv4_5->core_type = ARM_MODE_MON;
+
        (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
        armv4_5->core_cache = (*cache_p);
 }
 
 
-static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
-               struct target_s *target)
+static int cortex_a8_init_target(struct command_context *cmd_ctx,
+               struct target *target)
 {
        cortex_a8_build_reg_cache(target);
        return ERROR_OK;
 }
 
-int cortex_a8_init_arch_info(target_t *target,
+int cortex_a8_init_arch_info(struct target *target,
                struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
 {
-       armv4_5_common_t *armv4_5;
-       struct armv7a_common *armv7a;
-
-       armv7a = &cortex_a8->armv7a_common;
-       armv4_5 = &armv7a->armv4_5_common;
+       struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+       struct arm *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
        /* Setup struct cortex_a8_common */
        cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
        armv4_5->arch_info = armv7a;
 
-       armv4_5_init_arch_info(target, armv4_5);
-
        /* prepare JTAG information for the new target */
        cortex_a8->jtag_info.tap = tap;
        cortex_a8->jtag_info.scann_size = 4;
@@ -1505,19 +1502,17 @@ LOG_DEBUG(" ");
 
        armv4_5->read_core_reg = cortex_a8_read_core_reg;
        armv4_5->write_core_reg = cortex_a8_write_core_reg;
-//     armv4_5->full_context = arm7_9_full_context;
 
-//     armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
-//     armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
-//     armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
-//     armv4_5->write_core_reg = armv4_5_write_core_reg;
+       /* REVISIT v7a setup should be in a v7a-specific routine */
+       armv4_5_init_arch_info(target, armv4_5);
+       armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
        target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 
        return ERROR_OK;
 }
 
-static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
+static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
 {
        struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
 
@@ -1528,17 +1523,17 @@ static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
 
 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
 {
-       target_t *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
        struct armv7a_common *armv7a = target_to_armv7a(target);
 
-       return armv4_5_handle_cache_info_command(cmd_ctx,
+       return armv4_5_handle_cache_info_command(CMD_CTX,
                        &armv7a->armv4_5_mmu.armv4_5_cache);
 }
 
 
 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 {
-       target_t *target = get_current_target(cmd_ctx);
+       struct target *target = get_current_target(CMD_CTX);
 
        cortex_a8_init_debug_access(target);
 
@@ -1546,9 +1541,9 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 }
 
 
-static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
+static int cortex_a8_register_commands(struct command_context *cmd_ctx)
 {
-       command_t *cortex_a8_cmd;
+       struct command *cortex_a8_cmd;
        int retval = ERROR_OK;
 
        armv4_5_register_commands(cmd_ctx);
@@ -1569,7 +1564,7 @@ static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
        return retval;
 }
 
-target_type_t cortexa8_target = {
+struct target_type cortexa8_target = {
        .name = "cortex_a8",
 
        .poll = cortex_a8_poll,
@@ -1590,8 +1585,9 @@ target_type_t cortexa8_target = {
        .read_memory = cortex_a8_read_memory,
        .write_memory = cortex_a8_write_memory,
        .bulk_write_memory = cortex_a8_bulk_write_memory,
-       .checksum_memory = arm7_9_checksum_memory,
-       .blank_check_memory = arm7_9_blank_check_memory,
+
+       .checksum_memory = arm_checksum_memory,
+       .blank_check_memory = arm_blank_check_memory,
 
        .run_algorithm = armv4_5_run_algorithm,
 
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