armv7m_core_reg_t -> struct armv7m_core_reg

[openocd.git] / src / target / cortex_a8.h

diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index 358f71bfff6f817bd1a63536b0d661dae3a989c8..8216ffbb52386b240016871a25bde426f4e5e0f9 100644 (file)
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -53,6 +53,7 @@ extern char* cortex_a8_state_strings[];
 #define CPUDBG_BVR_BASE        0x100
 #define CPUDBG_BCR_BASE        0x140
 #define CPUDBG_WVR_BASE        0x180
+#define CPUDBG_WCR_BASE        0x1C0
 
 #define CPUDBG_OSLAR   0x300
 #define CPUDBG_OSLSR   0x304
@@ -79,6 +80,7 @@ extern char* cortex_a8_state_strings[];
 #define DSCR_MON_DBG_MODE              15
 #define DSCR_INSTR_COMP                24
 #define DSCR_DTR_TX_FULL               29
+#define DSCR_DTR_RX_FULL               30
 
 typedef struct  cortex_a8_brp_s
 {
@@ -101,12 +103,7 @@ typedef struct  cortex_a8_wrp_s
 typedef struct cortex_a8_common_s
 {
        int common_magic;
-       arm_jtag_t jtag_info;
-
-       /* Core Debug Unit */
-       uint32_t debug_base;
-       uint8_t debug_ap;
-       uint8_t memory_ap;
+       struct arm_jtag jtag_info;
 
        /* Context information */
        uint32_t cpudbg_dscr;
@@ -136,12 +133,17 @@ typedef struct cortex_a8_common_s
        /* Use cortex_a8_read_regs_through_mem for fast register reads */
        int fast_reg_read;
 
-       armv7a_common_t armv7a_common;
-       void *arch_info;
+       struct armv7a_common armv7a_common;
 } cortex_a8_common_t;
 
-extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
-int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+static inline struct cortex_a8_common_s *
+target_to_cortex_a8(struct target_s *target)
+{
+       return container_of(target->arch_info, struct cortex_a8_common_s,
+                       armv7a_common.armv4_5_common);
+}
+
+int cortex_a8_init_arch_info(target_t *target,
+               cortex_a8_common_t *cortex_a8, struct jtag_tap *tap);
 
 #endif /* CORTEX_A8_H */