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target/cortex_m: do not leak memory on reexamination
[openocd.git] / src / target / cortex_m.c
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index aafc097a011792d714bdc0731a2f5766cbd194d3..028bfd80850da5697ec00a03488d3d2fcffd3ed5 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -61,6 +61,7 @@
 /* forward declarations */
 static int cortex_m_store_core_reg_u32(struct target *target,
                uint32_t num, uint32_t value);
+static void cortex_m_dwt_free(struct target *target);
 
 static int cortexm_dap_read_coreregister_u32(struct target *target,
        uint32_t *value, int regnum)
@@ -473,7 +474,7 @@ static int cortex_m_debug_entry(struct target *target)
 
        LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
                arm_mode_name(arm->core_mode),
-               *(uint32_t *)(arm->pc->value),
+               buf_get_u32(arm->pc->value, 0, 32),
                target_state_name(target));
 
        if (armv7m->post_debug_entry) {
@@ -1262,6 +1263,11 @@ int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
 
+       if (breakpoint->length == 3) {
+               LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
+               breakpoint->length = 2;
+       }
+
        if ((breakpoint->length != 2)) {
                LOG_INFO("only breakpoints of two bytes length supported");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -1493,6 +1499,29 @@ static int cortex_m_load_core_reg_u32(struct target *target,
                        LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
                        break;
 
+               case ARMV7M_FPSCR:
+                       /* Floating-point Status and Registers */
+                       retval = target_write_u32(target, DCB_DCRSR, 0x21);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = target_read_u32(target, DCB_DCRDR, value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
+                       break;
+
+               case ARMV7M_S0 ... ARMV7M_S31:
+                       /* Floating-point Status and Registers */
+                       retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = target_read_u32(target, DCB_DCRDR, value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
+                                 (int)(num - ARMV7M_S0), *value);
+                       break;
+
                case ARMV7M_PRIMASK:
                case ARMV7M_BASEPRI:
                case ARMV7M_FAULTMASK:
@@ -1556,6 +1585,29 @@ static int cortex_m_store_core_reg_u32(struct target *target,
                        LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
                        break;
 
+               case ARMV7M_FPSCR:
+                       /* Floating-point Status and Registers */
+                       retval = target_write_u32(target, DCB_DCRDR, value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
+                       if (retval != ERROR_OK)
+                               return retval;
+                       LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
+                       break;
+
+               case ARMV7M_S0 ... ARMV7M_S31:
+                       /* Floating-point Status and Registers */
+                       retval = target_write_u32(target, DCB_DCRDR, value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
+                       if (retval != ERROR_OK)
+                               return retval;
+                       LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
+                                 (int)(num - ARMV7M_S0), value);
+                       break;
+
                case ARMV7M_PRIMASK:
                case ARMV7M_BASEPRI:
                case ARMV7M_FAULTMASK:
@@ -1641,14 +1693,20 @@ static int cortex_m_init_target(struct command_context *cmd_ctx,
 struct dwt_reg_state {
        struct target *target;
        uint32_t addr;
-       uint32_t value;         /* scratch/cache */
+       uint8_t value[4];               /* scratch/cache */
 };
 
 static int cortex_m_dwt_get_reg(struct reg *reg)
 {
        struct dwt_reg_state *state = reg->arch_info;
 
-       return target_read_u32(state->target, state->addr, &state->value);
+       uint32_t tmp;
+       int retval = target_read_u32(state->target, state->addr, &tmp);
+       if (retval != ERROR_OK)
+               return retval;
+
+       buf_set_u32(state->value, 0, 32, tmp);
+       return ERROR_OK;
 }
 
 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
@@ -1703,7 +1761,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg
 
        r->name = d->name;
        r->size = d->size;
-       r->value = &state->value;
+       r->value = state->value;
        r->arch_info = state;
        r->type = &dwt_reg_type;
 }
@@ -1776,6 +1834,27 @@ fail1:
         */
 }
 
+static void cortex_m_dwt_free(struct target *target)
+{
+       struct cortex_m_common *cm = target_to_cm(target);
+       struct reg_cache *cache = cm->dwt_cache;
+
+       free(cm->dwt_comparator_list);
+       cm->dwt_comparator_list = NULL;
+
+       if (cache) {
+               register_unlink_cache(&target->reg_cache, cache);
+
+               if (cache->reg_list) {
+                       for (size_t i = 0; i < cache->num_regs; i++)
+                               free(cache->reg_list[i].arch_info);
+                       free(cache->reg_list);
+               }
+               free(cache);
+       }
+       cm->dwt_cache = NULL;
+}
+
 #define MVFR0 0xe000ef40
 #define MVFR1 0xe000ef44
 
@@ -1828,6 +1907,17 @@ int cortex_m_examine(struct target *target)
                        armv7m->arm.is_armv6m = true;
                }
 
+               if (armv7m->fp_feature != FPv4_SP &&
+                   armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
+                       /* free unavailable FPU registers */
+                       size_t idx;
+                       for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
+                            idx < armv7m->arm.core_cache->num_regs;
+                            idx++)
+                               free(armv7m->arm.core_cache->reg_list[idx].value);
+                       armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
+               }
+
                if (i == 4 || i == 3) {
                        /* Cortex-M3/M4 has 4096 bytes autoincrement range */
                        armv7m->dap.tar_autoincr_block = (1 << 12);
@@ -1842,6 +1932,7 @@ int cortex_m_examine(struct target *target)
                cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
                cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
                cortex_m->fp_code_available = cortex_m->fp_num_code;
+               free(cortex_m->fp_comparator_list);
                cortex_m->fp_comparator_list = calloc(
                                cortex_m->fp_num_code + cortex_m->fp_num_lit,
                                sizeof(struct cortex_m_fp_comparator));
@@ -1860,6 +1951,7 @@ int cortex_m_examine(struct target *target)
                        cortex_m->fp_num_lit);
 
                /* Setup DWT */
+               cortex_m_dwt_free(target);
                cortex_m_dwt_setup(cortex_m, target);
 
                /* These hardware breakpoints only work for code in flash! */
@@ -1910,7 +2002,9 @@ static int cortex_m_target_request_data(struct target *target,
        uint32_t i;
 
        for (i = 0; i < (size * 4); i++) {
-               cortex_m_dcc_read(target, &data, &ctrl);
+               int retval = cortex_m_dcc_read(target, &data, &ctrl);
+               if (retval != ERROR_OK)
+                       return retval;
                buffer[i] = data;
        }
 
@@ -1929,8 +2023,11 @@ static int cortex_m_handle_target_request(void *priv)
        if (target->state == TARGET_RUNNING) {
                uint8_t data;
                uint8_t ctrl;
+               int retval;
 
-               cortex_m_dcc_read(target, &data, &ctrl);
+               retval = cortex_m_dcc_read(target, &data, &ctrl);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* check if we have data */
                if (ctrl & (1 << 0)) {
@@ -1938,12 +2035,12 @@ static int cortex_m_handle_target_request(void *priv)
 
                        /* we assume target is quick enough */
                        request = data;
-                       cortex_m_dcc_read(target, &data, &ctrl);
-                       request |= (data << 8);
-                       cortex_m_dcc_read(target, &data, &ctrl);
-                       request |= (data << 16);
-                       cortex_m_dcc_read(target, &data, &ctrl);
-                       request |= (data << 24);
+                       for (int i = 1; i <= 3; i++) {
+                               retval = cortex_m_dcc_read(target, &data, &ctrl);
+                               if (retval != ERROR_OK)
+                                       return retval;
+                               request |= ((uint32_t)data << (i * 8));
+                       }
                        target_request(target, request);
                }
        }
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