arm_adi_v5: do not deactivate power domains while trying to clear sticky error

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d1afbd569a6261f10b37f3a5fe6ccd24a57c378f..07fea51374c1b2475b7810b904c4aee728bc1bd1 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -42,7 +42,7 @@
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
- * Some differences:  M0/M1 doesn't have FBP remapping or the
+ * Some differences:  M0/M1 doesn't have FPB remapping or the
  * DWT tracing/profiling support.  (So the cycle counter will
  * not be usable; the other stuff isn't currently used here.)
  *
@@ -165,7 +165,7 @@ static int cortex_m_single_step_core(struct target *target)
        struct armv7m_common *armv7m = &cortex_m->armv7m;
        int retval;
 
-       /* Mask interrupts before clearing halt, if done already.  This avoids
+       /* Mask interrupts before clearing halt, if not done already.  This avoids
         * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
         * HALT can put the core into an unknown state.
         */
@@ -237,8 +237,11 @@ static int cortex_m_endreset_event(struct target *target)
                        return retval;
        }
 
-       /* clear any interrupt masking */
-       cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
+       /* Restore proper interrupt masking setting. */
+       if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
+               cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
+       else
+               cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
 
        /* Enable features controlled by ITM and DWT blocks, and catch only
         * the vectors we were told to pay attention to.
@@ -252,7 +255,7 @@ static int cortex_m_endreset_event(struct target *target)
                return retval;
 
        /* Paranoia: evidently some (early?) chips don't preserve all the
-        * debug state (including FBP, DWT, etc) across reset...
+        * debug state (including FPB, DWT, etc) across reset...
         */
 
        /* Enable FPB */
@@ -1274,7 +1277,7 @@ int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpo
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
 
-       /* REVISIT why check? FBP can be updated with core running ... */
+       /* REVISIT why check? FPB can be updated with core running ... */
        if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
@@ -1983,7 +1986,7 @@ int cortex_m_examine(struct target *target)
        /* stlink shares the examine handler but does not support
         * all its calls */
        if (!armv7m->stlink) {
-               if (cortex_m->apsel < 0) {
+               if (cortex_m->apsel == DP_APSEL_INVALID) {
                        /* Search for the MEM-AP */
                        retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
                        if (retval != ERROR_OK) {
@@ -2080,7 +2083,7 @@ int cortex_m_examine(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               if (armv7m->trace_config.config_type != DISABLED) {
+               if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
                        armv7m_trace_tpiu_config(target);
                        armv7m_trace_itm_config(target);
                }
@@ -2274,20 +2277,6 @@ static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
  * cortexm3_target structure, which is only used with CM3 targets.
  */
 
-static const struct {
-       char name[10];
-       unsigned mask;
-} vec_ids[] = {
-       { "hard_err",   VC_HARDERR, },
-       { "int_err",    VC_INTERR, },
-       { "bus_err",    VC_BUSERR, },
-       { "state_err",  VC_STATERR, },
-       { "chk_err",    VC_CHKERR, },
-       { "nocp_err",   VC_NOCPERR, },
-       { "mm_err",     VC_MMERR, },
-       { "reset",      VC_CORERESET, },
-};
-
 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 {
        struct target *target = get_current_target(CMD_CTX);
@@ -2296,6 +2285,20 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
        uint32_t demcr = 0;
        int retval;
 
+       static const struct {
+               char name[10];
+               unsigned mask;
+       } vec_ids[] = {
+               { "hard_err",   VC_HARDERR, },
+               { "int_err",    VC_INTERR, },
+               { "bus_err",    VC_BUSERR, },
+               { "state_err",  VC_STATERR, },
+               { "chk_err",    VC_CHKERR, },
+               { "nocp_err",   VC_NOCPERR, },
+               { "mm_err",     VC_MMERR, },
+               { "reset",      VC_CORERESET, },
+       };
+
        retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
        if (retval != ERROR_OK)
                return retval;