for (i = 0; i < num_regs; i++) {
r = &armv7m->arm.core_cache->reg_list[i];
- if (!r->valid)
+ if (r->exist && !r->valid)
arm->read_core_reg(target, r, i, ARM_MODE_ANY);
}
return ERROR_OK;
}
+int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
+{
+ if (target->debug_reason != DBG_REASON_WATCHPOINT)
+ return ERROR_FAIL;
+
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+
+ for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
+ if (!wp->set)
+ continue;
+
+ unsigned int dwt_num = wp->set - 1;
+ struct cortex_m_dwt_comparator *comparator = cortex_m->dwt_comparator_list + dwt_num;
+
+ uint32_t dwt_function;
+ int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
+ if (retval != ERROR_OK)
+ return ERROR_FAIL;
+
+ /* check the MATCHED bit */
+ if (dwt_function & BIT(24)) {
+ *hit_watchpoint = wp;
+ return ERROR_OK;
+ }
+ }
+
+ return ERROR_FAIL;
+}
+
void cortex_m_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
{
struct cortex_m_common *cortex_m = target_to_cm(target);
- armv7m_trace_tpiu_exit(target);
-
free(cortex_m->fp_comparator_list);
cortex_m_dwt_free(target);
/* test for floating point feature on Cortex-M4 */
if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
- armv7m->fp_feature = FPv4_SP;
+ armv7m->fp_feature = FPV4_SP;
}
} else if (i == 7 || i == 33 || i == 35 || i == 55) {
target_read_u32(target, MVFR0, &mvfr0);
/* test for floating point features on Cortex-M7 */
if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
- armv7m->fp_feature = FPv5_SP;
+ armv7m->fp_feature = FPV5_SP;
} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
- armv7m->fp_feature = FPv5_DP;
+ armv7m->fp_feature = FPV5_DP;
}
} else if (i == 0) {
/* Cortex-M0 does not support unaligned memory access */
armv7m->arm.is_armv6m = true;
}
- if (armv7m->fp_feature == FP_NONE &&
- armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
- /* free unavailable FPU registers */
- size_t idx;
+ /* Check for FPU, otherwise mark FPU register as non-existent */
+ if (armv7m->fp_feature == FP_NONE)
+ for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
+ armv7m->arm.core_cache->reg_list[idx].exist = false;
- for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
- idx < armv7m->arm.core_cache->num_regs;
- idx++) {
- free(armv7m->arm.core_cache->reg_list[idx].feature);
- free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
- }
- armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
- }
if (!armv7m->stlink) {
if (i == 3 || i == 4)
if (retval != ERROR_OK)
return retval;
- if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED)
- armv7m_trace_tpiu_config(target);
-
if (armv7m->trace_config.itm_deferred_config)
armv7m_trace_itm_config(target);
{
.chain = armv7m_trace_command_handlers,
},
+ /* START_DEPRECATED_TPIU */
+ {
+ .chain = arm_tpiu_deprecated_command_handlers,
+ },
+ /* END_DEPRECATED_TPIU */
{
.name = "cortex_m",
.mode = COMMAND_EXEC,
struct target_type cortexm_target = {
.name = "cortex_m",
- .deprecated_name = "cortex_m3",
.poll = cortex_m_poll,
.arch_state = armv7m_arch_state,
.remove_breakpoint = cortex_m_remove_breakpoint,
.add_watchpoint = cortex_m_add_watchpoint,
.remove_watchpoint = cortex_m_remove_watchpoint,
+ .hit_watchpoint = cortex_m_hit_watchpoint,
.commands = cortex_m_command_handlers,
.target_create = cortex_m_target_create,