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Add initial RTT support
[openocd.git] / src / target / cortex_m.c
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 00e7c3a5750a2cfeabd9b7403f6f5f1a5fd4422b..316089c3513a1359c1e2d8a45452968960b60a96 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -39,6 +39,7 @@
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
 #include <helper/time_support.h>
+#include <rtt/rtt.h>
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
@@ -56,8 +57,8 @@ static int cortex_m_store_core_reg_u32(struct target *target,
                uint32_t num, uint32_t value);
 static void cortex_m_dwt_free(struct target *target);
 
-static int cortexm_dap_read_coreregister_u32(struct target *target,
-       uint32_t *value, int regnum)
+static int cortex_m_load_core_reg_u32(struct target *target,
+               uint32_t regsel, uint32_t *value)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        int retval;
@@ -71,7 +72,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
                        return retval;
        }
 
-       retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
+       retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
        if (retval != ERROR_OK)
                return retval;
 
@@ -89,8 +90,8 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
        return retval;
 }
 
-static int cortexm_dap_write_coreregister_u32(struct target *target,
-       uint32_t value, int regnum)
+static int cortex_m_store_core_reg_u32(struct target *target,
+               uint32_t regsel, uint32_t value)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        int retval;
@@ -108,7 +109,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
+       retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
        if (retval != ERROR_OK)
                return retval;
 
@@ -527,12 +528,6 @@ static int cortex_m_debug_entry(struct target *target)
        r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
 
-       /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
-       if (xPSR & 0xf00) {
-               r->dirty = r->valid;
-               cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
-       }
-
        /* Are we in an exception handler */
        if (xPSR & 0x1FF) {
                armv7m->exception_number = (xPSR & 0x1FF);
@@ -823,15 +818,19 @@ static int cortex_m_resume(struct target *target, int current,
                 * in parallel with disabled interrupts can cause local faults
                 * to not be taken.
                 *
-                * REVISIT this clearly breaks non-debug execution, since the
-                * PRIMASK register state isn't saved/restored...  workaround
-                * by never resuming app code after debug execution.
+                * This breaks non-debug (application) execution if not
+                * called from armv7m_start_algorithm() which saves registers.
                 */
                buf_set_u32(r->value, 0, 1, 1);
                r->dirty = true;
                r->valid = true;
 
-               /* Make sure we are in Thumb mode */
+               /* Make sure we are in Thumb mode, set xPSR.T bit */
+               /* armv7m_start_algorithm() initializes entire xPSR register.
+                * This duplicity handles the case when cortex_m_resume()
+                * is used with the debug_execution flag directly,
+                * not called through armv7m_start_algorithm().
+                */
                r = armv7m->arm.cpsr;
                buf_set_u32(r->value, 24, 1, 1);
                r->dirty = true;
@@ -1204,11 +1203,13 @@ static int cortex_m_assert_reset(struct target *target)
                if (retval3 != ERROR_OK)
                        LOG_DEBUG("Ignoring AP write error right after reset");
 
-               retval3 = dap_dp_init(armv7m->debug_ap->dap);
-               if (retval3 != ERROR_OK)
+               retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
+               if (retval3 != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
-
-               else {
+                       /* The error return value must not be propagated in this case.
+                        * SYSRESETREQ or VECTRESET have been possibly triggered
+                        * so reset processing should continue */
+               } else {
                        /* I do not know why this is necessary, but it
                         * fixes strange effects (step/resume cause NMI
                         * after reset) on LM3S6918 -- Michael Schwingen
@@ -1251,7 +1252,8 @@ static int cortex_m_deassert_reset(struct target *target)
        if ((jtag_reset_config & RESET_HAS_SRST) &&
            !(jtag_reset_config & RESET_SRST_NO_GATING) &&
                target_was_examined(target)) {
-               int retval = dap_dp_init(armv7m->debug_ap->dap);
+
+               int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
                if (retval != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
                        return retval;
@@ -1606,117 +1608,6 @@ void cortex_m_enable_watchpoints(struct target *target)
        }
 }
 
-static int cortex_m_load_core_reg_u32(struct target *target,
-               uint32_t regsel, uint32_t *value)
-{
-       int retval;
-
-       switch (regsel) {
-               case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
-                       /* read a normal core register */
-                       retval = cortexm_dap_read_coreregister_u32(target, value, regsel);
-
-                       if (retval != ERROR_OK) {
-                               LOG_ERROR("JTAG failure %i", retval);
-                               return ERROR_JTAG_DEVICE_ERROR;
-                       }
-                       LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
-                       break;
-
-               case ARMV7M_REGSEL_FPSCR:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_read_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
-                       break;
-
-               case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRSR, regsel);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_read_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
-                                 (int)(regsel - ARMV7M_REGSEL_S0), *value);
-                       break;
-
-               case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
-                       retval = cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
-                       if (retval != ERROR_OK)
-                               return retval;
-
-                       LOG_DEBUG("load from special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, *value);
-                       break;
-
-               default:
-                       return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-
-       return ERROR_OK;
-}
-
-static int cortex_m_store_core_reg_u32(struct target *target,
-               uint32_t regsel, uint32_t value)
-{
-       int retval;
-       struct armv7m_common *armv7m = target_to_armv7m(target);
-
-       switch (regsel) {
-               case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
-                       retval = cortexm_dap_write_coreregister_u32(target, value, regsel);
-                       if (retval != ERROR_OK) {
-                               struct reg *r;
-
-                               LOG_ERROR("JTAG failure");
-                               r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
-                               r->dirty = r->valid;
-                               return ERROR_JTAG_DEVICE_ERROR;
-                       }
-                       LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
-                       break;
-
-               case ARMV7M_REGSEL_FPSCR:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
-                       break;
-
-               case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_write_u32(target, DCB_DCRSR, regsel | DCRSR_WnR);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
-                                 (int)(regsel - ARMV7M_REGSEL_S0), value);
-                       break;
-
-               case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
-                       cortexm_dap_write_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
-
-                       LOG_DEBUG("write special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, value);
-                       break;
-
-               default:
-                       return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-
-       return ERROR_OK;
-}
-
 static int cortex_m_read_memory(struct target *target, target_addr_t address,
        uint32_t size, uint32_t count, uint8_t *buffer)
 {
@@ -2155,7 +2046,6 @@ int cortex_m_examine(struct target *target)
                        for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
                             idx < armv7m->arm.core_cache->num_regs;
                             idx++) {
-                               free(armv7m->arm.core_cache->reg_list[idx].value);
                                free(armv7m->arm.core_cache->reg_list[idx].feature);
                                free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
                        }
@@ -2600,6 +2490,9 @@ static const struct command_registration cortex_m_command_handlers[] = {
                .usage = "",
                .chain = cortex_m_exec_command_handlers,
        },
+       {
+               .chain = rtt_target_command_handlers,
+       },
        COMMAND_REGISTRATION_DONE
 };
 
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