Add initial RTT support

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 7b3f3c70e31d6fc20e559db9de9c31fc47937be1..316089c3513a1359c1e2d8a45452968960b60a96 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -39,6 +39,7 @@
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
 #include <helper/time_support.h>
+#include <rtt/rtt.h>
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
@@ -527,12 +528,6 @@ static int cortex_m_debug_entry(struct target *target)
        r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
 
-       /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
-       if (xPSR & 0xf00) {
-               r->dirty = r->valid;
-               cortex_m_store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, xPSR & ~0xff);
-       }
-
        /* Are we in an exception handler */
        if (xPSR & 0x1FF) {
                armv7m->exception_number = (xPSR & 0x1FF);
@@ -823,15 +818,19 @@ static int cortex_m_resume(struct target *target, int current,
                 * in parallel with disabled interrupts can cause local faults
                 * to not be taken.
                 *
-                * REVISIT this clearly breaks non-debug execution, since the
-                * PRIMASK register state isn't saved/restored...  workaround
-                * by never resuming app code after debug execution.
+                * This breaks non-debug (application) execution if not
+                * called from armv7m_start_algorithm() which saves registers.
                 */
                buf_set_u32(r->value, 0, 1, 1);
                r->dirty = true;
                r->valid = true;
 
-               /* Make sure we are in Thumb mode */
+               /* Make sure we are in Thumb mode, set xPSR.T bit */
+               /* armv7m_start_algorithm() initializes entire xPSR register.
+                * This duplicity handles the case when cortex_m_resume()
+                * is used with the debug_execution flag directly,
+                * not called through armv7m_start_algorithm().
+                */
                r = armv7m->arm.cpsr;
                buf_set_u32(r->value, 24, 1, 1);
                r->dirty = true;
@@ -1204,11 +1203,13 @@ static int cortex_m_assert_reset(struct target *target)
                if (retval3 != ERROR_OK)
                        LOG_DEBUG("Ignoring AP write error right after reset");
 
-               retval3 = dap_dp_init(armv7m->debug_ap->dap);
-               if (retval3 != ERROR_OK)
+               retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
+               if (retval3 != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
-
-               else {
+                       /* The error return value must not be propagated in this case.
+                        * SYSRESETREQ or VECTRESET have been possibly triggered
+                        * so reset processing should continue */
+               } else {
                        /* I do not know why this is necessary, but it
                         * fixes strange effects (step/resume cause NMI
                         * after reset) on LM3S6918 -- Michael Schwingen
@@ -1251,7 +1252,8 @@ static int cortex_m_deassert_reset(struct target *target)
        if ((jtag_reset_config & RESET_HAS_SRST) &&
            !(jtag_reset_config & RESET_SRST_NO_GATING) &&
                target_was_examined(target)) {
-               int retval = dap_dp_init(armv7m->debug_ap->dap);
+
+               int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
                if (retval != ERROR_OK) {
                        LOG_ERROR("DP initialisation failed");
                        return retval;
@@ -2488,6 +2490,9 @@ static const struct command_registration cortex_m_command_handlers[] = {
                .usage = "",
                .chain = cortex_m_exec_command_handlers,
        },
+       {
+               .chain = rtt_target_command_handlers,
+       },
        COMMAND_REGISTRATION_DONE
 };