server, target, cortex_m: add deinit_target to the API to free resources

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index b194c33e6f1baa07e9f83a481391e5250cf87219..4dc92c834e549395f91758a88d99d102c2444fd8 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -61,6 +61,7 @@
 /* forward declarations */
 static int cortex_m_store_core_reg_u32(struct target *target,
                uint32_t num, uint32_t value);
+static void cortex_m_dwt_free(struct target *target);
 
 static int cortexm_dap_read_coreregister_u32(struct target *target,
        uint32_t *value, int regnum)
@@ -1684,6 +1685,15 @@ static int cortex_m_init_target(struct command_context *cmd_ctx,
        return ERROR_OK;
 }
 
+void cortex_m_deinit_target(struct target *target)
+{
+       struct cortex_m_common *cortex_m = target_to_cm(target);
+
+       free(cortex_m->fp_comparator_list);
+       cortex_m_dwt_free(target);
+       free(cortex_m);
+}
+
 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
  * on r/w if the core is not running, and clear on resume or reset ... or
  * at least, in a post_restore_context() method.
@@ -1833,6 +1843,27 @@ fail1:
         */
 }
 
+static void cortex_m_dwt_free(struct target *target)
+{
+       struct cortex_m_common *cm = target_to_cm(target);
+       struct reg_cache *cache = cm->dwt_cache;
+
+       free(cm->dwt_comparator_list);
+       cm->dwt_comparator_list = NULL;
+
+       if (cache) {
+               register_unlink_cache(&target->reg_cache, cache);
+
+               if (cache->reg_list) {
+                       for (size_t i = 0; i < cache->num_regs; i++)
+                               free(cache->reg_list[i].arch_info);
+                       free(cache->reg_list);
+               }
+               free(cache);
+       }
+       cm->dwt_cache = NULL;
+}
+
 #define MVFR0 0xe000ef40
 #define MVFR1 0xe000ef44
 
@@ -1885,6 +1916,17 @@ int cortex_m_examine(struct target *target)
                        armv7m->arm.is_armv6m = true;
                }
 
+               if (armv7m->fp_feature != FPv4_SP &&
+                   armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
+                       /* free unavailable FPU registers */
+                       size_t idx;
+                       for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
+                            idx < armv7m->arm.core_cache->num_regs;
+                            idx++)
+                               free(armv7m->arm.core_cache->reg_list[idx].value);
+                       armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
+               }
+
                if (i == 4 || i == 3) {
                        /* Cortex-M3/M4 has 4096 bytes autoincrement range */
                        armv7m->dap.tar_autoincr_block = (1 << 12);
@@ -1899,6 +1941,7 @@ int cortex_m_examine(struct target *target)
                cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
                cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
                cortex_m->fp_code_available = cortex_m->fp_num_code;
+               free(cortex_m->fp_comparator_list);
                cortex_m->fp_comparator_list = calloc(
                                cortex_m->fp_num_code + cortex_m->fp_num_lit,
                                sizeof(struct cortex_m_fp_comparator));
@@ -1917,6 +1960,7 @@ int cortex_m_examine(struct target *target)
                        cortex_m->fp_num_lit);
 
                /* Setup DWT */
+               cortex_m_dwt_free(target);
                cortex_m_dwt_setup(cortex_m, target);
 
                /* These hardware breakpoints only work for code in flash! */
@@ -2327,4 +2371,5 @@ struct target_type cortexm_target = {
        .target_create = cortex_m_target_create,
        .init_target = cortex_m_init_target,
        .examine = cortex_m_examine,
+       .deinit_target = cortex_m_deinit_target,
 };