target: arm: disassembler: fix Thumb2 BLX decoding address

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 11dbf24f28eb871fffd7ed05ebfb6875a37acd53..79af632ac7faca703292f02055072b1fb033738a 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -168,12 +168,8 @@ static int cortex_m_single_step_core(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
        struct armv7m_common *armv7m = &cortex_m->armv7m;
-       uint32_t dhcsr_save;
        int retval;
 
-       /* backup dhcsr reg */
-       dhcsr_save = cortex_m->dcb_dhcsr;
-
        /* Mask interrupts before clearing halt, if done already.  This avoids
         * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
         * HALT can put the core into an unknown state.
@@ -191,7 +187,6 @@ static int cortex_m_single_step_core(struct target *target)
        LOG_DEBUG(" ");
 
        /* restore dhcsr reg */
-       cortex_m->dcb_dhcsr = dhcsr_save;
        cortex_m_clear_halt(target);
 
        return ERROR_OK;
@@ -1712,6 +1707,97 @@ void cortex_m_deinit_target(struct target *target)
        free(cortex_m);
 }
 
+int cortex_m_profiling(struct target *target, uint32_t *samples,
+                             uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
+{
+       struct timeval timeout, now;
+       struct armv7m_common *armv7m = target_to_armv7m(target);
+       uint32_t reg_value;
+       bool use_pcsr = false;
+       int retval = ERROR_OK;
+       struct reg *reg;
+
+       gettimeofday(&timeout, NULL);
+       timeval_add_time(&timeout, seconds, 0);
+
+       retval = target_read_u32(target, DWT_PCSR, &reg_value);
+       if (retval != ERROR_OK) {
+               LOG_ERROR("Error while reading PCSR");
+               return retval;
+       }
+
+       if (reg_value != 0) {
+               use_pcsr = true;
+               LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
+       } else {
+               LOG_INFO("Starting profiling. Halting and resuming the"
+                        " target as often as we can...");
+               reg = register_get_by_name(target->reg_cache, "pc", 1);
+       }
+
+       /* Make sure the target is running */
+       target_poll(target);
+       if (target->state == TARGET_HALTED)
+               retval = target_resume(target, 1, 0, 0, 0);
+
+       if (retval != ERROR_OK) {
+               LOG_ERROR("Error while resuming target");
+               return retval;
+       }
+
+       uint32_t sample_count = 0;
+
+       for (;;) {
+               if (use_pcsr) {
+                       if (armv7m && armv7m->debug_ap) {
+                               uint32_t read_count = max_num_samples - sample_count;
+                               if (read_count > 1024)
+                                       read_count = 1024;
+
+                               retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
+                                                       (void *)&samples[sample_count],
+                                                       4, read_count, DWT_PCSR);
+                               sample_count += read_count;
+                       } else {
+                               target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
+                       }
+               } else {
+                       target_poll(target);
+                       if (target->state == TARGET_HALTED) {
+                               reg_value = buf_get_u32(reg->value, 0, 32);
+                               /* current pc, addr = 0, do not handle breakpoints, not debugging */
+                               retval = target_resume(target, 1, 0, 0, 0);
+                               samples[sample_count++] = reg_value;
+                               target_poll(target);
+                               alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
+                       } else if (target->state == TARGET_RUNNING) {
+                               /* We want to quickly sample the PC. */
+                               retval = target_halt(target);
+                       } else {
+                               LOG_INFO("Target not halted or running");
+                               retval = ERROR_OK;
+                               break;
+                       }
+               }
+
+               if (retval != ERROR_OK) {
+                       LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
+                       return retval;
+               }
+
+
+               gettimeofday(&now, NULL);
+               if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
+                       LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
+                       break;
+               }
+       }
+
+       *num_samples = sample_count;
+       return retval;
+}
+
+
 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
  * on r/w if the core is not running, and clear on resume or reset ... or
  * at least, in a post_restore_context() method.
@@ -2456,4 +2542,6 @@ struct target_type cortexm_target = {
        .init_target = cortex_m_init_target,
        .examine = cortex_m_examine,
        .deinit_target = cortex_m_deinit_target,
+
+       .profiling = cortex_m_profiling,
 };