/* NOTE: most of this should work fine for the Cortex-M1 and
* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
- * Some differences: M0/M1 doesn't have FBP remapping or the
+ * Some differences: M0/M1 doesn't have FPB remapping or the
* DWT tracing/profiling support. (So the cycle counter will
* not be usable; the other stuff isn't currently used here.)
*
* any longer.
*/
-/**
- * Returns the type of a break point required by address location
- */
-#define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
-
/* forward declarations */
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value);
struct armv7m_common *armv7m = &cortex_m->armv7m;
int retval;
- /* Mask interrupts before clearing halt, if done already. This avoids
+ /* Mask interrupts before clearing halt, if not done already. This avoids
* Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
* HALT can put the core into an unknown state.
*/
return retval;
}
- /* clear any interrupt masking */
- cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
+ /* Restore proper interrupt masking setting. */
+ if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
+ cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
+ else
+ cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
/* Enable features controlled by ITM and DWT blocks, and catch only
* the vectors we were told to pay attention to.
return retval;
/* Paranoia: evidently some (early?) chips don't preserve all the
- * debug state (including FBP, DWT, etc) across reset...
+ * debug state (including FPB, DWT, etc) across reset...
*/
/* Enable FPB */
return retval;
}
- cortex_m->fpb_enabled = 1;
+ cortex_m->fpb_enabled = true;
/* Restore FPB registers */
for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
}
if (cortex_m->dcb_dhcsr & S_RESET_ST) {
- target->state = TARGET_RESET;
+ if (target->state != TARGET_RESET) {
+ target->state = TARGET_RESET;
+ LOG_INFO("%s: external reset detected", target_name(target));
+ }
return ERROR_OK;
}
}
}
+ /* Check that target is truly halted, since the target could be resumed externally */
+ if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
+ /* registers are now invalid */
+ register_cache_invalidate(armv7m->arm.core_cache);
+
+ target->state = TARGET_RUNNING;
+ LOG_WARNING("%s: external resume detected", target_name(target));
+ target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ retval = ERROR_OK;
+ }
+
/* Did we detect a failure condition that we cleared? */
if (detected_failure != ERROR_OK)
retval = detected_failure;
else {
/* Set a temporary break point */
- if (breakpoint)
+ if (breakpoint) {
retval = cortex_m_set_breakpoint(target, breakpoint);
- else
- retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
+ } else {
+ enum breakpoint_type type = BKPT_HARD;
+ if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
+ /* FPB rev.1 cannot handle such addr, try BKPT instr */
+ type = BKPT_SOFT;
+ }
+ retval = breakpoint_add(target, pc_value, 2, type);
+ }
+
bool tmp_bp_set = (retval == ERROR_OK);
/* No more breakpoints left, just do a step */
retval = ERROR_OK;
} else {
/* Use a standard Cortex-M3 software reset mechanism.
- * We default to using VECRESET as it is supported on all current cores.
+ * We default to using VECRESET as it is supported on all current cores
+ * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
* This has the disadvantage of not resetting the peripherals, so a
* reset-init event handler is needed to perform any peripheral resets.
*/
+ if (!cortex_m->vectreset_supported
+ && reset_config == CORTEX_M_RESET_VECTRESET) {
+ reset_config = CORTEX_M_RESET_SYSRESETREQ;
+ LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
+ LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
+ }
+
LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
? "SYSRESETREQ" : "VECTRESET");
return ERROR_OK;
}
- if (cortex_m->auto_bp_type)
- breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-
if (breakpoint->type == BKPT_HARD) {
uint32_t fpcr_value;
while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
breakpoint->set = fp_num + 1;
fpcr_value = breakpoint->address | 1;
if (cortex_m->fp_rev == 0) {
+ if (breakpoint->address > 0x1FFFFFFF) {
+ LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
+ return ERROR_FAIL;
+ }
uint32_t hilo;
hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
return ERROR_FAIL;
}
- comparator_list[fp_num].used = 1;
+ comparator_list[fp_num].used = true;
comparator_list[fp_num].fpcr_value = fpcr_value;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
return retval;
}
- cortex_m->fpb_enabled = 1;
+ cortex_m->fpb_enabled = true;
}
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
LOG_DEBUG("Invalid FP Comparator number in breakpoint");
return ERROR_OK;
}
- comparator_list[fp_num].used = 0;
+ comparator_list[fp_num].used = false;
comparator_list[fp_num].fpcr_value = 0;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
} else {
/* restore original instruction (kept in target endianness) */
- if (breakpoint->length == 4) {
- retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
+ retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
+ breakpoint->length, 1,
breakpoint->orig_instr);
- if (retval != ERROR_OK)
- return retval;
- } else {
- retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
- breakpoint->orig_instr);
- if (retval != ERROR_OK)
- return retval;
- }
+ if (retval != ERROR_OK)
+ return retval;
}
breakpoint->set = false;
{
struct cortex_m_common *cortex_m = target_to_cm(target);
- if (cortex_m->auto_bp_type)
- breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-
- if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
- if (breakpoint->type == BKPT_HARD) {
- LOG_INFO("flash patch comparator requested outside code memory region");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- if (breakpoint->type == BKPT_SOFT) {
- LOG_INFO("soft breakpoint requested in code (flash) memory region");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
- }
-
if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
{
struct cortex_m_common *cortex_m = target_to_cm(target);
- /* REVISIT why check? FBP can be updated with core running ... */
+ /* REVISIT why check? FPB can be updated with core running ... */
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (cortex_m->auto_bp_type)
- breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-
if (breakpoint->set)
cortex_m_unset_breakpoint(target, breakpoint);
LOG_ERROR("Can not find free DWT Comparator");
return ERROR_FAIL;
}
- comparator->used = 1;
+ comparator->used = true;
watchpoint->set = dwt_num + 1;
comparator->comp = watchpoint->address;
}
comparator = cortex_m->dwt_comparator_list + dwt_num;
- comparator->used = 0;
+ comparator->used = false;
comparator->function = 0;
target_write_u32(target, comparator->dwt_comparator_address + 8,
comparator->function);
free(cortex_m);
}
-static int cortex_m_profiling(struct target *target, uint32_t *samples,
+int cortex_m_profiling(struct target *target, uint32_t *samples,
uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
{
struct timeval timeout, now;
for (;;) {
if (use_pcsr) {
- uint32_t read_count = max_num_samples - sample_count;
- if (read_count > 1024)
- read_count = 1024;
- retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
+ if (armv7m && armv7m->debug_ap) {
+ uint32_t read_count = max_num_samples - sample_count;
+ if (read_count > 1024)
+ read_count = 1024;
+
+ retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
(void *)&samples[sample_count],
4, read_count, DWT_PCSR);
- sample_count += read_count;
+ sample_count += read_count;
+ } else {
+ target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
+ }
} else {
target_poll(target);
if (target->state == TARGET_HALTED) {
gettimeofday(&now, NULL);
- if (sample_count >= max_num_samples ||
- (now.tv_sec >= timeout.tv_sec && now.tv_usec >= timeout.tv_usec)) {
+ if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
break;
}
struct dwt_reg {
uint32_t addr;
- char *name;
+ const char *name;
unsigned size;
};
-static struct dwt_reg dwt_base_regs[] = {
+static const struct dwt_reg dwt_base_regs[] = {
{ DWT_CTRL, "dwt_ctrl", 32, },
/* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
* increments while the core is asleep.
/* plus some 8 bit counters, useful for profiling with TPIU */
};
-static struct dwt_reg dwt_comp[] = {
+static const struct dwt_reg dwt_comp[] = {
#define DWT_COMPARATOR(i) \
{ DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
{ DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
DWT_COMPARATOR(1),
DWT_COMPARATOR(2),
DWT_COMPARATOR(3),
+ DWT_COMPARATOR(4),
+ DWT_COMPARATOR(5),
+ DWT_COMPARATOR(6),
+ DWT_COMPARATOR(7),
+ DWT_COMPARATOR(8),
+ DWT_COMPARATOR(9),
+ DWT_COMPARATOR(10),
+ DWT_COMPARATOR(11),
+ DWT_COMPARATOR(12),
+ DWT_COMPARATOR(13),
+ DWT_COMPARATOR(14),
+ DWT_COMPARATOR(15),
#undef DWT_COMPARATOR
};
.set = cortex_m_dwt_set_reg,
};
-static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
+static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
{
struct dwt_reg_state *state;
int reg, i;
target_read_u32(target, DWT_CTRL, &dwtcr);
+ LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
if (!dwtcr) {
LOG_DEBUG("no DWT");
return;
/* stlink shares the examine handler but does not support
* all its calls */
if (!armv7m->stlink) {
- retval = dap_dp_init(swjdp);
- if (retval != ERROR_OK) {
- LOG_ERROR("Could not initialize the debug port");
- return retval;
- }
-
- if (cortex_m->apsel < 0) {
+ if (cortex_m->apsel == DP_APSEL_INVALID) {
/* Search for the MEM-AP */
retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
if (retval != ERROR_OK) {
}
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
+ /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
+ cortex_m->vectreset_supported = i > 1;
+
if (i == 4) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
if (retval != ERROR_OK)
return retval;
- if (armv7m->trace_config.config_type != DISABLED) {
+ if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
armv7m_trace_tpiu_config(target);
armv7m_trace_itm_config(target);
}
/* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr);
- cortex_m->auto_bp_type = 1;
/* bits [14:12] and [7:4] */
cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
}
static int cortex_m_init_arch_info(struct target *target,
- struct cortex_m_common *cortex_m, struct jtag_tap *tap)
+ struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
{
struct armv7m_common *armv7m = &cortex_m->armv7m;
armv7m_init_arch_info(target, armv7m);
- /* tap has no dap initialized */
- if (!tap->dap) {
- tap->dap = dap_init();
-
- /* Leave (only) generic DAP stuff for debugport_init() */
- tap->dap->tap = tap;
- }
-
/* default reset mode is to use srst if fitted
* if not it will use CORTEX_M3_RESET_VECTRESET */
cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
- armv7m->arm.dap = tap->dap;
+ armv7m->arm.dap = dap;
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
- target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
+ target_register_timer_callback(cortex_m_handle_target_request, 1,
+ TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
{
+ struct adiv5_private_config *pc;
+
+ pc = (struct adiv5_private_config *)target->private_config;
+ if (adiv5_verify_config(pc) != ERROR_OK)
+ return ERROR_FAIL;
+
struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
+ if (cortex_m == NULL) {
+ LOG_ERROR("No memory creating target");
+ return ERROR_FAIL;
+ }
cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
- cortex_m_init_arch_info(target, cortex_m, target->tap);
+ cortex_m->apsel = pc->ap_num;
- if (target->private_config != NULL) {
- struct adiv5_private_config *pc =
- (struct adiv5_private_config *)target->private_config;
- cortex_m->apsel = pc->ap_num;
- } else
- cortex_m->apsel = -1;
+ cortex_m_init_arch_info(target, cortex_m, pc->dap);
return ERROR_OK;
}
* cortexm3_target structure, which is only used with CM3 targets.
*/
-static const struct {
- char name[10];
- unsigned mask;
-} vec_ids[] = {
- { "hard_err", VC_HARDERR, },
- { "int_err", VC_INTERR, },
- { "bus_err", VC_BUSERR, },
- { "state_err", VC_STATERR, },
- { "chk_err", VC_CHKERR, },
- { "nocp_err", VC_NOCPERR, },
- { "mm_err", VC_MMERR, },
- { "reset", VC_CORERESET, },
-};
-
COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
{
struct target *target = get_current_target(CMD_CTX);
uint32_t demcr = 0;
int retval;
+ static const struct {
+ char name[10];
+ unsigned mask;
+ } vec_ids[] = {
+ { "hard_err", VC_HARDERR, },
+ { "int_err", VC_INTERR, },
+ { "bus_err", VC_BUSERR, },
+ { "state_err", VC_STATERR, },
+ { "chk_err", VC_CHKERR, },
+ { "nocp_err", VC_NOCPERR, },
+ { "mm_err", VC_MMERR, },
+ { "reset", VC_CORERESET, },
+ };
+
retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
if (retval != ERROR_OK)
return retval;
if (CMD_ARGC > 0) {
if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
- else if (strcmp(*CMD_ARGV, "vectreset") == 0)
- cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
+
+ else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
+ if (target_was_examined(target)
+ && !cortex_m->vectreset_supported)
+ LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
+ else
+ cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
+
+ } else
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
switch (cortex_m->soft_reset_config) {
.handler = handle_cortex_m_reset_config_command,
.mode = COMMAND_ANY,
.help = "configure software reset handling",
- .usage = "['srst'|'sysresetreq'|'vectreset']",
+ .usage = "['sysresetreq'|'vectreset']",
},
COMMAND_REGISTRATION_DONE
};
.deassert_reset = cortex_m_deassert_reset,
.soft_reset_halt = cortex_m_soft_reset_halt,
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = armv7m_get_gdb_reg_list,
.read_memory = cortex_m_read_memory,
Code Review / openocd.git / blobdiff