cortex_m: dwt_num_comp should be set to zero in cortex_m_dwt_free()

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 028bfd80850da5697ec00a03488d3d2fcffd3ed5..88b226d85c8ad86e6167ad7a67a0fdb457b18b2f 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1053,12 +1053,6 @@ static int cortex_m_assert_reset(struct target *target)
                 * This has the disadvantage of not resetting the peripherals, so a
                 * reset-init event handler is needed to perform any peripheral resets.
                 */
-               retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
-                               AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
-                               ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
-               if (retval != ERROR_OK)
-                       return retval;
-
                LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
                        ? "SYSRESETREQ" : "VECTRESET");
 
@@ -1067,17 +1061,16 @@ static int cortex_m_assert_reset(struct target *target)
                                "handler to reset any peripherals or configure hardware srst support.");
                }
 
-               /*
-                 SAM4L needs to execute security initalization
-                 startup sequence before AP access would be enabled.
-                 During the intialization CDBGPWRUPACK is pulled low and we
-                 need to wait for it to be set to 1 again.
-               */
-               retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT,
-                                             CDBGPWRUPACK, CDBGPWRUPACK, 100);
+               retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+                               AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
+                               ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
+               if (retval != ERROR_OK)
+                       LOG_DEBUG("Ignoring AP write error right after reset");
+
+               retval = ahbap_debugport_init(swjdp);
                if (retval != ERROR_OK) {
-                       LOG_ERROR("Failed waitnig for CDBGPWRUPACK");
-                       return ERROR_FAIL;
+                       LOG_ERROR("DP initialisation failed");
+                       return retval;
                }
 
                {
@@ -1114,6 +1107,17 @@ static int cortex_m_deassert_reset(struct target *target)
        /* deassert reset lines */
        adapter_deassert_reset();
 
+       enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+       if ((jtag_reset_config & RESET_HAS_SRST) &&
+           !(jtag_reset_config & RESET_SRST_NO_GATING)) {
+               int retval = ahbap_debugport_init(target_to_cm(target)->armv7m.arm.dap);
+               if (retval != ERROR_OK) {
+                       LOG_ERROR("DP initialisation failed");
+                       return retval;
+               }
+       }
+
        return ERROR_OK;
 }
 
@@ -1121,7 +1125,6 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 {
        int retval;
        int fp_num = 0;
-       uint32_t hilo;
        struct cortex_m_common *cortex_m = target_to_cm(target);
        struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
 
@@ -1134,6 +1137,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
 
        if (breakpoint->type == BKPT_HARD) {
+               uint32_t fpcr_value;
                while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
                        fp_num++;
                if (fp_num >= cortex_m->fp_num_code) {
@@ -1141,9 +1145,17 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
                        return ERROR_FAIL;
                }
                breakpoint->set = fp_num + 1;
-               hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
+               fpcr_value = breakpoint->address | 1;
+               if (cortex_m->fp_rev == 0) {
+                       uint32_t hilo;
+                       hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
+                       fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
+               } else if (cortex_m->fp_rev > 1) {
+                       LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
+                       return ERROR_FAIL;
+               }
                comparator_list[fp_num].used = 1;
-               comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
+               comparator_list[fp_num].fpcr_value = fpcr_value;
                target_write_u32(target, comparator_list[fp_num].fpcr_address,
                        comparator_list[fp_num].fpcr_value);
                LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
@@ -1685,6 +1697,18 @@ static int cortex_m_init_target(struct command_context *cmd_ctx,
        return ERROR_OK;
 }
 
+void cortex_m_deinit_target(struct target *target)
+{
+       struct cortex_m_common *cortex_m = target_to_cm(target);
+
+       free(cortex_m->fp_comparator_list);
+
+       cortex_m_dwt_free(target);
+       armv7m_free_reg_cache(target);
+
+       free(cortex_m);
+}
+
 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
  * on r/w if the core is not running, and clear on resume or reset ... or
  * at least, in a post_restore_context() method.
@@ -1841,6 +1865,7 @@ static void cortex_m_dwt_free(struct target *target)
 
        free(cm->dwt_comparator_list);
        cm->dwt_comparator_list = NULL;
+       cm->dwt_num_comp = 0;
 
        if (cache) {
                register_unlink_cache(&target->reg_cache, cache);
@@ -1911,10 +1936,14 @@ int cortex_m_examine(struct target *target)
                    armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
                        /* free unavailable FPU registers */
                        size_t idx;
+
                        for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
                             idx < armv7m->arm.core_cache->num_regs;
-                            idx++)
+                            idx++) {
                                free(armv7m->arm.core_cache->reg_list[idx].value);
+                               free(armv7m->arm.core_cache->reg_list[idx].feature);
+                               free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
+                       }
                        armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
                }
 
@@ -1923,6 +1952,16 @@ int cortex_m_examine(struct target *target)
                        armv7m->dap.tar_autoincr_block = (1 << 12);
                }
 
+               /* Configure trace modules */
+               retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
+               if (retval != ERROR_OK)
+                       return retval;
+
+               if (armv7m->trace_config.config_type != DISABLED) {
+                       armv7m_trace_tpiu_config(target);
+                       armv7m_trace_itm_config(target);
+               }
+
                /* NOTE: FPB and DWT are both optional. */
 
                /* Setup FPB */
@@ -1932,6 +1971,9 @@ int cortex_m_examine(struct target *target)
                cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
                cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
                cortex_m->fp_code_available = cortex_m->fp_num_code;
+               /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
+                  Revision is zero base, fp_rev == 1 means Rev.2 ! */
+               cortex_m->fp_rev = (fpcr >> 28) & 0xf;
                free(cortex_m->fp_comparator_list);
                cortex_m->fp_comparator_list = calloc(
                                cortex_m->fp_num_code + cortex_m->fp_num_lit,
@@ -2315,6 +2357,9 @@ static const struct command_registration cortex_m_command_handlers[] = {
        {
                .chain = armv7m_command_handlers,
        },
+       {
+               .chain = armv7m_trace_command_handlers,
+       },
        {
                .name = "cortex_m",
                .mode = COMMAND_EXEC,
@@ -2362,4 +2407,5 @@ struct target_type cortexm_target = {
        .target_create = cortex_m_target_create,
        .init_target = cortex_m_init_target,
        .examine = cortex_m_examine,
+       .deinit_target = cortex_m_deinit_target,
 };